Commit Graph

13604 Commits

Author SHA1 Message Date
Nathan Hartman
5b813f0c14 arch/stm32l4: Fix nxstyle errors
arch/arm/include/stm32l4/stm32l4x3xx_irq.h:
arch/arm/include/stm32l4/stm32l4xrxx_irq.h:

    * Fix nxstyle errors.
2021-03-17 21:49:30 +01:00
Xiang Xiao
335ba21657 arch/arm: Fix syscall number out of swi range in thumb mode
The immediate number is 8bits in thumb mode:
+---------------------+---------------+
|15 14 13 12 11 10 9 8|7 6 5 4 3 2 1 0|
+---------------------+---------------+
| 1  1  0  1  1  1 1 1|      imm8     |
+---------------------+---------------+

The immediate number is 24bits in arm mode:
+-----------+-------------------------------------------------------------------------+
|31 30 29 28|27 26 25 24|23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|
+-----------+-----------+-------------------------------------------------------------+
|   cond    | 1  1  1  1|                                imm24                        |
+-----------+-----------+-------------------------------------------------------------+

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I62503cdc377fcee81864e88e981d389bce2e1b45
2021-03-17 14:52:58 -03:00
Jiuzhu Dong
e96c8b9283 fs: allocate file/socket dynamically
Change-Id: I8aea63eaf0275f47f21fc8d5482b51ffecd5c906
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-03-17 06:46:42 -07:00
SPRESENSE
2f29521dd1 cxd56_cpu1signal: Fix an issue that gnss does not work
Because a thread of gnss receiver is created by pthread in the
AppBringUp task, the thread would be killed when AppBringUp
task exits.
Change to use kthread_create instead of pthread_create to prevent
this issue.
2021-03-17 06:36:33 -07:00
SPRESENSE
f7047d8ea3 cxd56_gnss: Add missing include header for cxd56_gnss.c
cxd56_gnss.c uses file descriptor operation from next change.
 0536953 Kernel module should prefer functions with nx/kmm prefix

But this change need to add fcntl.h in include header.
So, add missing header.
2021-03-17 03:11:54 -07:00
YAMAMOTO Takashi
9bd10898d2 arch/arm/src/lc823450: Make LC823450_IPL2 select BCH 2021-03-17 01:25:16 -07:00
Peter van der Perk
4dd457854d [FlexCAN] Correct reset state for CTRL1 register 2021-03-16 19:50:58 -07:00
Nathan Hartman
f165270a80 arch/stm32l4: Fix nxstyle errors
arch/arm/include/stm32l4/chip.h:
arch/arm/include/stm32l4/irq.h:
arch/arm/include/stm32l4/stm32l4x5xx_irq.h:
arch/arm/include/stm32l4/stm32l4x6xx_irq.h:

    * Fix nxstyle errors.
2021-03-16 19:38:30 -07:00
Michael Jung
b3ab373f3a stm32l5: Fix findings with latest nxstyle
Fix some incorrect relative file paths in ASF headers found with the
latest version of nxstyle.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Michael Jung
fb14125320 stm32l5: Coding style fixes
Put blanks around the '+' in register address definitions.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Michael Jung
3581289661 stm32l5: Put a timeout on waiting for LSE
Do not run into an infinite loop if the LSE does not start up.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Michael Jung
c031e4d2ee stm32l562xx_pinmap.h: Coding style fix
Remove spaces around binary-or operators in GPIO defines everywhere to
get a consistent coding style.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Michael Jung
8e14cb6065 stm32l5: Remove drive strengths from GPIO defines
As proposed by David Sidrane.  Required drive strength is board specific
and should be defined in the respective board.h file.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Michael Jung
78a69a89d8 stm32l5: Remove unused CACHE_LINESIZE defines
Cortex-M33 does neither have an I- nor a D-Cache.  Both defines are not
used across the stm32l5 architecture code.  Thus, just remove them.

_Originally posted by @acassis in https://github.com/apache/incubator-nuttx/pull/2974#discussion_r588224862_

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Michael Jung
33892dcc54 armv8-m/arm_svcall.c: Fix compiler warning
regs[REG_R0] is uint32_t type, but '%d' expects int type.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Michael Jung
f3a5675cc4 stm32l5: Architecture Support for STM32L5
Architecture support for STMicroelectronics STM32L552xx and STM32L562xx
MCUs.  This is based on corresponding code for STM32L4, but has been
considerably adjusted.  Tested with Nucleo-L552ZE-Q and STM32L562E-DK
boards with simple NSH configurations.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-16 12:04:00 -07:00
Nathan Hartman
13816de7ac arch/stm32f7: Fix nxstyle errors
arch/arm/include/stm32f7/chip.h:
arch/arm/include/stm32f7/irq.h:
arch/arm/include/stm32f7/stm32f72xx73xx_irq.h:
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h:
arch/arm/include/stm32f7/stm32f76xx77xx_irq.h:

    * Fix nxstyle errors.
2021-03-15 17:01:31 +01:00
Masayuki Ishikawa
73786e71ff arch: sam34: Author Masayuki Ishikawa: Update license to Apache
Signed-off-by: Masayuki Ishikawa <asayuki.Ishikawa@jp.sony.com>
2021-03-14 22:23:05 -07:00
Yuichi Nakamura
40fe666d3f arm/rp2040: Fix SPI halfword DMA transfer 2021-03-14 22:21:22 -07:00
Alin Jerpelea
f7c11c92c3 arch: Makefile: Alan Carvalho de Assis: update licenses to Apache
Alan Carvalho de Assis has submitted the SGA and we can migrate the licenses
 to Apache.

Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-13 05:56:43 -08:00
Alin Jerpelea
bd94263a33 arch: Makefile: Author Gregory Nutt: update licenses to Apache
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-13 05:56:43 -08:00
David Sidrane
0c57351f78 mmcsd:Stuck in 1-bit mode, Removed CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
mmcsd:Remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   stm32h7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   stm32f7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   stm32f7:sdmmc WRITE COMPLETE prevent false triggers
   stm32h7:sdmmc WRITE COMPLETE prevent false triggers

   While testing PR #2989 on the H7 I noticed that the cards
   were staying in 1-bit mode. The root cause was that the
   scr read path was using DMA without an invlidate.

   This was caused by CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT,
   but the sdmmc driver, did not use the delayed invalidate
   nor would it work on 8 bytes.

   The driver fully supported dcache mgt on runt buffers, but
   the #ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT blocked it.

   Reviewing the PR that added CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT
   it may have been valid at the time. But after the dcache operations
   we fixed. It is not necessary and offers no benefit.
2021-03-12 16:42:16 -03:00
Nathan Hartman
6061981e37 arch/stm32h7: Fix nxstyle errors
arch/arm/include/stm32h7/irq.h:
arch/arm/include/stm32h7/stm32h7x7xx_irq.h:

    * Fix nxstyle errors.
2021-03-12 16:58:51 +00:00
Masayuki Ishikawa
9aaa4068c1 arch: imx6: Fix an error message in imx_enet.c
Summary:
- This commit fixes an error message in imx_enet.c

Impact:
- None

Testing:
- Build only

Suggested-by: David Sidrane <David.Sidrane@NscDg.com>
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-03-12 11:30:08 +08:00
Yuichi Nakamura
174a4c1b68 arm/rp2040: Add RP2040 GPIO interrupt functions 2021-03-11 19:31:17 -03:00
Nathan Hartman
9fd0df3931 arch/stm32: Fix nxstyle errors
arch/arm/include/stm32/stm32f10xxx_irq.h:
arch/arm/include/stm32/stm32f20xxx_irq.h:
arch/arm/include/stm32/stm32f30xxx_irq.h:
arch/arm/include/stm32/stm32f33xxx_irq.h:
arch/arm/include/stm32/stm32f37xxx_irq.h:
arch/arm/include/stm32/stm32l15xxx_irq.h:

    * Fix nxstyle errors.
2021-03-11 21:39:27 +00:00
Masayuki Ishikawa
ad094552f8 arch: cxd56xx: Add CONFIG_ARCH_LEDS_CPU_ACTIVITY to cxd56_idle.c and cxd56_irq.c
Summary:
- This commit adds CPU activity LED feature to cxd56_idle.c and cx56_irq.c
- An LED for the current CPU will turn off before calling WFI
- An LED for the current CPU will turn on when an interrupt happens

Impact:
- CONFIG_ARCH_LEDS_CPU_ACTIVITY=y only

Testing:
- defconfigs will be commited later.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-03-11 15:30:38 +01:00
Masayuki Ishikawa
2c753be0df Revert "arch: cxd56xx: Fix cxd56_usbdev.c for SMP"
Summary:
- The original commit was added to avoid hardfault but the
  root cause was the stack corruption which has been fixed by
  the previous commit. So let me revert the original commit.

Impact:
- SMP only

Testing:
- spresense:rndis_smp with nxplayer + telnet

This reverts commit 197187d826.

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-03-10 14:14:52 +08:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
Gustavo Henrique Nihei
47cb41c92f makefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
Yuichi Nakamura
938b1daf02 arm/rp2040: RP2040 SPI DMA transfer support 2021-03-08 17:37:48 -03:00
Yuichi Nakamura
b69df289bd arm/rp2040: Add RP2040 DMAC functions 2021-03-08 17:37:48 -03:00
Anthony Merlino
892b6393e3 stm32h7x7xx: Setup UART1 and UART6 clocks as part of APB2 bringup if enabled. 2021-03-08 01:51:54 -08:00
Anthony Merlino
3705202b85 Fix missing IO_CONFIG setting for STM32H747XI 2021-03-08 01:51:54 -08:00
Yuichi Nakamura
2d7aabf13b arm/rp2040: Add RP2040 SPI device support 2021-03-08 17:06:07 +09:00
Yuichi Nakamura
a8d269df98 arm/rp2040: Add rp2040_gpio_init/put/get/setdir() 2021-03-08 17:06:07 +09:00
Anthony Merlino
40217e644f stm32h7: Allow custom clock configuration to use stdclockconfig 2021-03-07 23:40:29 -08:00
Masayuki Ishikawa
197187d826 arch: cxd56xx: Fix cxd56_usbdev.c for SMP
Summary:
- This commit fixes hardfault when running nxplayer with rndis_smp

Impact:
- SMP only

Testing:
- Tested with rndis_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-03-07 19:51:12 -08:00
Anthony Merlino
67b9f5f9e3 Fix nxstyle issues.
# Conflicts:
#	arch/arm/src/armv7-m/dwt.h
2021-03-07 02:35:56 -08:00
Anthony Merlino
afd6ad4ff5 arch/armv7-m: Adds dwt helper functions for controlling watchpoints in code.
In scenarios where there is suspicion that someone might be touching your data when you don't expect, you can setup a watchpoint, and then guard accesses that you know are valid. If the debugger halts due to the watchpoint, you'll see where the unexpected access is coming from.
2021-03-07 02:35:56 -08:00
David Sidrane
da2f9f1357 stm32h7:Ethernet Fixed hardfaults, from too big frames 2021-03-06 03:07:58 -08:00
David Sidrane
ac2e35bb0f stm32f7:Ethernet Fixed hardfaults, from too big frames 2021-03-06 03:07:58 -08:00
David Sidrane
abda656076 stm32:Ethernet Fix too big frames 2021-03-06 03:07:58 -08:00
Peter Bee
e223f60c09 net/socket: move si_send/recv into sendmsg/recvmsg
Implement si_send/sendto/recvfrom with si_sendmsg/recvmsg, instead of
the other way round.

Change-Id: I7b858556996e0862df22807a6edf6d7cfe6518fc
Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2021-03-05 04:46:13 -08:00
David Sidrane
8b73e30185 arch/arm/src/stm32h7/Kconfig
stm32h7:lse fix Kconfig help text
2021-03-04 07:10:18 -08:00
David Sidrane
296d94b5cb stm32f7:lse Use Kconfig values directly 2021-03-04 00:16:10 -08:00
Fotis Panagiotopoulos
f423403dfa stm32_wwdg debug log formatting 2021-03-03 19:02:04 -08:00
Nathan Hartman
3ac61053ce arch/stm32, arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32/hardware/stm32_dma2d.h,
arch/arm/src/stm32/hardware/stm32_ltdc.h,
arch/arm/src/stm32/stm32_dma2d.c,
arch/arm/src/stm32/stm32_ltdc.c,
arch/arm/src/stm32f7/hardware/stm32_dma2d.h,
arch/arm/src/stm32f7/hardware/stm32_ltdc.h,
arch/arm/src/stm32f7/stm32_dma2d.c, and
arch/arm/src/stm32f7/stm32_ltdc.c:

    * Fix nxstyle "mixed case identifier" errors for the
      following identifiers:

      DMA2D_xGPFCCR_ALPHA         -> DMA2D_XGPFCCR_ALPHA
      DMA2D_xGPFCCR_AM            -> DMA2D_XGPFCCR_AM
      DMA2D_xGPFCCR_CCM           -> DMA2D_XGPFCCR_CCM
      DMA2D_xGPFCCR_CM            -> DMA2D_XGPFCCR_CM
      DMA2D_xGPFCCR_CS            -> DMA2D_XGPFCCR_CS
      DMA2D_xGPFCCR_START         -> DMA2D_XGPFCCR_START
      LTDC_LxBFCR_BF1             -> LTDC_LXBFCR_BF1
      LTDC_LxBFCR_BF2             -> LTDC_LXBFCR_BF2
      LTDC_LxCFBLR_CFBLL          -> LTDC_LXCFBLR_CFBLL
      LTDC_LxCFBLR_CFBP           -> LTDC_LXCFBLR_CFBP
      LTDC_LxCR_CLUTEN            -> LTDC_LXCR_CLUTEN
      LTDC_LxCR_COLKEN            -> LTDC_LXCR_COLKEN
      LTDC_LxCR_LEN               -> LTDC_LXCR_LEN
      LTDC_LxWHPCR_WHSPPOS        -> LTDC_LXWHPCR_WHSPPOS
      LTDC_LxWHPCR_WHSTPOS        -> LTDC_LXWHPCR_WHSTPOS
      LTDC_LxWVPCR_WVSPPOS        -> LTDC_LXWVPCR_WVSPPOS
      LTDC_LxWVPCR_WVSTPOS        -> LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_LxWHPCR_WHSTPOS  -> STM32_LTDC_LXWHPCR_WHSTPOS
      STM32_LTDC_LxWVPCR_WVSTPOS  -> STM32_LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_Lx_BYPP          -> STM32_LTDC_LX_BYPP
      DMA2D_xGCOLR_BLUE           -> DMA2D_XGCOLR_BLUE
      DMA2D_xGCOLR_BLUE_MASK      -> DMA2D_XGCOLR_BLUE_MASK
      DMA2D_xGCOLR_BLUE_SHIFT     -> DMA2D_XGCOLR_BLUE_SHIFT
      DMA2D_xGCOLR_GREEN          -> DMA2D_XGCOLR_GREEN
      DMA2D_xGCOLR_GREEN_MASK     -> DMA2D_XGCOLR_GREEN_MASK
      DMA2D_xGCOLR_GREEN_SHIFT    -> DMA2D_XGCOLR_GREEN_SHIFT
      DMA2D_xGCOLR_RED            -> DMA2D_XGCOLR_RED
      DMA2D_xGCOLR_RED_MASK       -> DMA2D_XGCOLR_RED_MASK
      DMA2D_xGCOLR_RED_SHIFT      -> DMA2D_XGCOLR_RED_SHIFT
      DMA2D_xGOR                  -> DMA2D_XGOR
      DMA2D_xGOR_MASK             -> DMA2D_XGOR_MASK
      DMA2D_xGOR_SHIFT            -> DMA2D_XGOR_SHIFT
      DMA2D_xGPFCCR_ALPHA_MASK    -> DMA2D_XGPFCCR_ALPHA_MASK
      DMA2D_xGPFCCR_ALPHA_SHIFT   -> DMA2D_XGPFCCR_ALPHA_SHIFT
      DMA2D_xGPFCCR_AM_MASK       -> DMA2D_XGPFCCR_AM_MASK
      DMA2D_xGPFCCR_AM_SHIFT      -> DMA2D_XGPFCCR_AM_SHIFT
      DMA2D_xGPFCCR_CM_MASK       -> DMA2D_XGPFCCR_CM_MASK
      DMA2D_xGPFCCR_CM_SHIFT      -> DMA2D_XGPFCCR_CM_SHIFT
      DMA2D_xGPFCCR_CS_MASK       -> DMA2D_XGPFCCR_CS_MASK
      DMA2D_xGPFCCR_CS_SHIFT      -> DMA2D_XGPFCCR_CS_SHIFT
      LTDC_LxBFCR_BF1_MASK        -> LTDC_LXBFCR_BF1_MASK
      LTDC_LxBFCR_BF1_SHIFT       -> LTDC_LXBFCR_BF1_SHIFT
      LTDC_LxBFCR_BF2_MASK        -> LTDC_LXBFCR_BF2_MASK
      LTDC_LxBFCR_BF2_SHIFT       -> LTDC_LXBFCR_BF2_SHIFT
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA_MASK     -> LTDC_LXCACR_CONSTA_MASK
      LTDC_LxCACR_CONSTA_SHIFT    -> LTDC_LXCACR_CONSTA_SHIFT
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN_MASK       -> LTDC_LXCFBLNR_LN_MASK
      LTDC_LxCFBLNR_LN_SHIFT      -> LTDC_LXCFBLNR_LN_SHIFT
      LTDC_LxCFBLR_CFBLL_MASK     -> LTDC_LXCFBLR_CFBLL_MASK
      LTDC_LxCFBLR_CFBLL_SHIFT    -> LTDC_LXCFBLR_CFBLL_SHIFT
      LTDC_LxCFBLR_CFBP_MASK      -> LTDC_LXCFBLR_CFBP_MASK
      LTDC_LxCFBLR_CFBP_SHIFT     -> LTDC_LXCFBLR_CFBP_SHIFT
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE_MASK     -> LTDC_LXCKCR_CKBLUE_MASK
      LTDC_LxCKCR_CKBLUE_SHIFT    -> LTDC_LXCKCR_CKBLUE_SHIFT
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN_MASK    -> LTDC_LXCKCR_CKGREEN_MASK
      LTDC_LxCKCR_CKGREEN_SHIFT   -> LTDC_LXCKCR_CKGREEN_SHIFT
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED_MASK      -> LTDC_LXCKCR_CKRED_MASK
      LTDC_LxCKCR_CKRED_SHIFT     -> LTDC_LXCKCR_CKRED_SHIFT
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE_MASK     -> LTDC_LXCLUTWR_BLUE_MASK
      LTDC_LxCLUTWR_BLUE_SHIFT    -> LTDC_LXCLUTWR_BLUE_SHIFT
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD_MASK  -> LTDC_LXCLUTWR_CLUTADD_MASK
      LTDC_LxCLUTWR_CLUTADD_SHIFT -> LTDC_LXCLUTWR_CLUTADD_SHIFT
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN_MASK    -> LTDC_LXCLUTWR_GREEN_MASK
      LTDC_LxCLUTWR_GREEN_SHIFT   -> LTDC_LXCLUTWR_GREEN_SHIFT
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED_MASK      -> LTDC_LXCLUTWR_RED_MASK
      LTDC_LxCLUTWR_RED_SHIFT     -> LTDC_LXCLUTWR_RED_SHIFT
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA_MASK    -> LTDC_LXDCCR_DCALPHA_MASK
      LTDC_LxDCCR_DCALPHA_SHIFT   -> LTDC_LXDCCR_DCALPHA_SHIFT
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE_MASK     -> LTDC_LXDCCR_DCBLUE_MASK
      LTDC_LxDCCR_DCBLUE_SHIFT    -> LTDC_LXDCCR_DCBLUE_SHIFT
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN_MASK    -> LTDC_LXDCCR_DCGREEN_MASK
      LTDC_LxDCCR_DCGREEN_SHIFT   -> LTDC_LXDCCR_DCGREEN_SHIFT
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED_MASK      -> LTDC_LXDCCR_DCRED_MASK
      LTDC_LxDCCR_DCRED_SHIFT     -> LTDC_LXDCCR_DCRED_SHIFT
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF_MASK         -> LTDC_LXPFCR_PF_MASK
      LTDC_LxPFCR_PF_SHIFT        -> LTDC_LXPFCR_PF_SHIFT
      LTDC_LxWHPCR_WHSPPOS_MASK   -> LTDC_LXWHPCR_WHSPPOS_MASK
      LTDC_LxWHPCR_WHSPPOS_SHIFT  -> LTDC_LXWHPCR_WHSPPOS_SHIFT
      LTDC_LxWHPCR_WHSTPOS_MASK   -> LTDC_LXWHPCR_WHSTPOS_MASK
      LTDC_LxWHPCR_WHSTPOS_SHIFT  -> LTDC_LXWHPCR_WHSTPOS_SHIFT
      LTDC_LxWVPCR_WVSPPOS_MASK   -> LTDC_LXWVPCR_WVSPPOS_MASK
      LTDC_LxWVPCR_WVSPPOS_SHIFT  -> LTDC_LXWVPCR_WVSPPOS_SHIFT
      LTDC_LxWVPCR_WVSTPOS_MASK   -> LTDC_LXWVPCR_WVSTPOS_MASK
      LTDC_LxWVPCR_WVSTPOS_SHIFT  -> LTDC_LXWVPCR_WVSTPOS_SHIFT

    * Fix all other nxstyle errors in the affected files.
2021-03-03 18:49:20 -08:00
ligd
f9d20ea4d2 sigdeliver: fix system block when kill signal to idle in SMP
Bug description:

CONFIG_SMP=y

Suppose we have 2 cores in SMP, here is the ps return:

PID GROUP CPU PRI POLICY TYPE    NPX STATE     STACK   USED  FILLED COMMAND
  0     0   0   0 FIFO   Kthread N-- Assigned 004076 000748  18.3%  CPU0 IDLE
  1     0   1   0 FIFO   Kthread N-- Running  004096 000540  13.1%  CPU1 IDLE

nsh> kill -4 0
or:
nsh> kill -4 1

system blocked.

Reason:

In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.

Fix:

Add condition to cover saved_irqcount == 0.

Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-03-03 15:03:32 +00:00
Yuichi Nakamura
9d0b3594f6 arm/rp2040: Add RP2040 I2C device support 2021-03-03 09:35:45 -03:00
Yuichi Nakamura
60b18467f3 arm/rp2040: Add rp2040_gpio_set_pulls() 2021-03-03 09:35:45 -03:00
David Sidrane
ab5f46d46c stm32h7:Add DBGMCU 2021-03-02 18:28:19 -08:00
Nathan Hartman
a3f0923ad0 arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32f7/stm32_tim.h:

    * Fix nxstyle errors.
2021-03-02 21:34:33 +00:00
David Sidrane
1e5754232a stm32f7:Add option to auto select LSE CAPABILITY
This Knob will cycle through the values from
   low to high. To avoid damaging the crystal.
   We want to use the lowest setting that gets
   the OSC running. See app note AN2867
2021-03-02 14:34:56 -03:00
David Sidrane
9fbd7f9dc5 stm32h7:Add option to auto select LSE CAPABILITY
This Knob will cycle through the correct*
   values from low to high. To avoid damaging
   the crystal. We want to use the lowest setting
   that gets the OSC running. See app note AN2867

    *It will take into account the rev of the silicon
    and use the correct code points to achive the drive
    strength. See Eratta ES0392 Rev 7 2.2.14 LSE oscillator
    driving capability selection bits are swapped.
2021-03-02 14:34:56 -03:00
Michael Jung
fbfddda28b armv8-m: Fix EXC_RETURN for non-secure usage
With TrustZone support in armv8-m the bit-fields in EXC_RETURN have been
extended.  Bit 6 ('S') now specifies whether the interrupted program was
running in the Non-Secure (S=0) or Secure (S=1) security state.
Furthermore, Bit 0 ('ES' - Exception Secure) specifies the
security state athe exception is taken to (0: Non-Secure, 1: Secure).

When NuttX is run together with TrustedFirmware-M as the application in
the non-secure world both the S and the ES bits have to be set to '0'.
For armv8-m those are also the correct values if TrustZone is not
implemented on the respective MCU or if it is disabled.

Signed-off-by: Michael Jung <mijung@gmx.net>
2021-03-02 07:28:42 -03:00
Nathan Hartman
75eb3e8ec2 arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32f7/stm32_lowputc.c:

    * Fix nxstyle errors.
2021-03-01 18:13:06 +00:00
Xiang Xiao
3d24288a66 arm/cxd56xx: Beautify the coding style in cxd56_gnss.c
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-01 10:00:13 -05:00
Xiang Xiao
9473434587 Ensure the kernel component don't call userspace API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-01 09:23:09 +09:00
Masayuki Ishikawa
ef1826e133 arch: armv6-m: Apply armv7-m signal handling logic
Summary:
- This commit applies armv7-m signal handling logic

Impact:
- armv6-m signal handling

Testing:
- Tested with ostest with the following configs
- raspberrypi-pico:nsh, raspberrypi-pico:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-26 22:23:03 -06:00
Fotis Panagiotopoulos
40fdf388bd Fixed __stack_overflow_trap declaration typo. 2021-02-26 12:08:16 -08:00
Nathan Hartman
9d48beb2c8 arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32f7/stm32_ltdc.h,
arch/arm/src/stm32f7/stm32_pm.h,
arch/arm/src/stm32f7/stm32_pmsleep.c,
arch/arm/src/stm32f7/stm32_pmstandby.c,
arch/arm/src/stm32f7/stm32_pmstop.c,
arch/arm/src/stm32f7/stm32_pwm.h:

    * Fix nxstyle errors.
2021-02-26 17:13:05 +00:00
Peter van der Perk
4842868be2 [FlexCAN] Fix TX drop #2792 and correctly set CAN timings to non-zeroed registers 2021-02-26 06:14:33 -08:00
Michal Lenc
04fc5e314d arch/arm/src/imxrt: updated flexcan driver to support classical and FD frames at once
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2021-02-25 22:31:04 -08:00
Yuichi Nakamura
a556bbf3a4 arm/rp2040: Fix LDFLAGS for boot stage2 2021-02-25 11:25:27 -08:00
Masayuki Ishikawa
8085010ae8 arch: arm: Add 'select ARM_HAVE_WFE_SEV' to ARCH_CHIP_RP2040
Summary:
- This commit adds 'select ARM_HAVE_WFE_SEV' to ARCH_CHIP_RP2040
- Now NuttX spinlock uses WFE/SEV to reduce power consumption
- Also, modify a comment on rp2040

Impact:
- rp2040 only

Testing:
- Tested with raspberrypi-pico:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-24 19:12:22 -08:00
Nathan Hartman
7c5174a53b arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32f7/stm32_config.h,
arch/arm/src/stm32f7/stm32_dma.h,
arch/arm/src/stm32f7/stm32_dma2d.h,
arch/arm/src/stm32f7/stm32_dtcm.h,
arch/arm/src/stm32f7/stm32_dumpgpio.c,
arch/arm/src/stm32f7/stm32_ethernet.h,
arch/arm/src/stm32f7/stm32_gpio.c,
arch/arm/src/stm32f7/stm32_gpio.h:

    * Fix nxstyle errors.
2021-02-24 22:39:49 +00:00
Yuichi Nakamura
01699e00e0 arm/rp2040: Raspberry Pi Pico SMP support 2021-02-25 07:20:59 +09:00
David Sidrane
62321fa5db s32k1xx:Support ramfunc 2021-02-23 18:11:41 -08:00
Nathan Hartman
c90fffcc09 arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32f7/stm32_pwr.c,
arch/arm/src/stm32f7/stm32_pwr.h,
arch/arm/src/stm32f7/stm32_usbhost.h:

    * Fix nxstyle errors.
2021-02-22 18:18:58 -08:00
Yuichi Nakamura
7b8c72ec1b boards: raspberrypi-pico: Add nshsram defconfig for SRAM build 2021-02-22 09:11:09 -08:00
Masayuki Ishikawa
cf72133d3c rp2040: Continue to build even if PICO_SDK_PATH is not set
Summary:
- In the previous implementation, the build system stops if
  PICO_SDK_PATH is not set.
- However, this behavior is not good for CI. Because the path
  is only used to generate a flash image.
- This commit fixes this issue

Impact:
- rp2040 only

Testing:
- Tested with and without PICO_SDK_PATH
2021-02-21 20:30:58 -08:00
Alexander Vasiljev
8bb50b578b arch/stm32h7: add definitions for DAC 2021-02-21 07:39:05 -08:00
Yuichi Nakamura
96a473d39d arch/arm: Add support for boot stage2 from Raspberry Pi Pico SDK 2021-02-20 03:45:24 -08:00
Yuichi Nakamura
ed1da60f52 arch/arm: Add RP2040 (Raspberry Pi Pico's SoC) support 2021-02-20 03:45:24 -08:00
Yuichi Nakamura
d0002b24c7 arm: ARMv6-M vector table offset register support 2021-02-19 19:24:09 -08:00
Byron Ellacott
9a1b726bae fs: change geometry types from size_t to blkcnt_t and blksize_t
This change reflects that the geometry isn't related to the largest
allocatable unit on the platform.

Calls to read and write block devices are also affected and have
been updated.
2021-02-18 20:38:22 -08:00
Gustavo Henrique Nihei
7750de72bb stdint.h: Use conversion macros for the definition of MIN and MAX constants 2021-02-18 18:35:35 -08:00
Augusto Fraga Giachero
43a98662f3 lpc17xx_40xx/lpc17_40_i2c.c: Propagate I2C I/O errors
Check if all messages were transferred, if not, return -ENXIO.

This is particularly useful when the slave returns an unexpected NAK,
the application code should catch the error to avoid failing silently.
2021-02-18 18:33:05 -08:00
Brennan Ashton
9f1017feb3 board/freedom-k64f: Add usbdev support with cdcacm example 2021-02-14 19:51:34 -08:00
Nathan Hartman
01248cae8d arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32f7/stm32_qencoder.c,
arch/arm/src/stm32f7/stm32_rng.c,
arch/arm/src/stm32f7/stm32_rtc.c,
arch/arm/src/stm32f7/stm32_rtc.h,
arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c,
arch/arm/src/stm32f7/stm32_sai.h,
arch/arm/src/stm32f7/stm32_sdmmc.h,
arch/arm/src/stm32f7/stm32_spi.h,
arch/arm/src/stm32f7/stm32_tim_lowerhalf.c,
arch/arm/src/stm32f7/stm32_uid.c,
arch/arm/src/stm32f7/stm32_userspace.c,
arch/arm/src/stm32f7/stm32_userspace.h,
arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c,
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c:

    * Fix nxstyle errors.
2021-02-12 10:27:13 -08:00
Masayuki Ishikawa
c024b414f8 arch: cxd56xx: Introduce driver-specific spinlock in cxd56_serial.c
Summary:
- This commit introduces driver-specific spinlock in cxd56_serial.c
  to improve performance

Impact:
- SMP only

Testing:
- Tested with spresense:wifi and spresense:wifi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-09 11:29:18 -08:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs.
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-07 21:28:56 -08:00
Masayuki Ishikawa
96d4bc11c0 arch: s32k1xx: Fix style warnings in s32k1xx_edma.c
Summary:
- This commit fixes style warnings in s32k1xx_edma.c

Impact:
- None

Testing:
- N/A

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-04 21:49:16 -08:00
Masayuki Ishikawa
9f414cf6db arch: max32660: Fix style warnings and compile errors
Summary:
- This commit fixes style warnings under max32660
- Also fix compile errors in max32660_gpio.c with CONFIG_DEBUG_GPIO_INFO=y

Impact:
- None

Testing:
- Built with max32660-evsys:nsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-04 21:49:16 -08:00
Masayuki Ishikawa
dabd835bb7 arch: imxrt: Fix style warnings in imxrt_edma.[c,h]
Summary:
- This commit fixes style warnings in imxrt_edna.[c,y]

Impact:
- None

Testing:
- N/A

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-04 21:49:16 -08:00
Masayuki Ishikawa
12a515ebb6 arch: imxrt: Introduce CONFIG_NET_GUARDSIZE to imxrt_enet.c
Summary:
- In the previous imxrt_enet.c, imxrt_enet.c assumed that
  CONFIG_NET_ETH_PKTSIZE includes the ethernet CRC (4bytes)
- However, most of the driver implementation explicitly
  add CONFIG_NET_GUARDSIZE for the CRC to the internal buffer
- This commit conforms to such rules

Imapct:
- No impact

Testing:
- Tested with iperf with imxrt1060-evk
- NOTE: need to add the following configs
  +CONFIG_EXAMPLES_IPERF=y
  +CONFIG_EXAMPLES_IPERFTEST_DEVNAME="eth0"
  +CONFIG_IOB_NBUFFERS=128
  +CONFIG_NET_ETH_PKTSIZE=1514
  +CONFIG_NET_GUARDSIZE=4
  +CONFIG_RR_INTERVAL=200

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-04 00:29:07 -08:00
Huang Qi
aabb870d6b stm32f7/stm32_qspi.c: Fix warning of format strings
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-02-03 08:49:46 +00:00
David Sidrane
18ce105e8b stm32f412:Corrected Pin count
Port C was not working because the GPIO pin count was
   wrong. The 48 pin packages has 34 GPIO (Not counting PH0 & PH1)
   It is GPIOA GPIO B (sans PB11) and GPIOC PC13-PC15
2021-02-02 18:41:39 -08:00
Matias N
45b392be7e nRF52: add support for building SoftDevice BLE controller 2021-02-02 14:40:26 -08:00
Matias N
74e7e2b5b2 nRF52 tickless RTC: fix timer not firing on edge case
The calls via RTC API weren't fast enough for the edge case
of minimum counter value, resulting in the timer never
expiring as the counter had already passed the compare value.
This now uses direct register access functions and also
gets the latest counter value in edge case.
2021-02-02 14:37:22 -08:00
Matias N
27ac9a6948 nRF52 SPI: fix for RX transfers when !SPI_EXCHANGE 2021-02-02 14:37:22 -08:00
Matias N
e9a45ea183 nRF52 SPI: use PPI API instead of direct register access 2021-02-02 14:37:22 -08:00
Peter van der Perk
22437698f1 [imxrt] Fix FlexCAN tx dropping frames 2021-02-02 17:51:29 -03:00
Pavel Pisa
56be7c54ea arch/arm/src/samv7/sam_mcan.c: fix some mismatches caused by renaming.
The MCAN driver private structure has been renamed to struct sam_mcan_s,
but some functions reference sam_can_s. There are missing defines
of return variable in some functions.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
2021-02-01 18:28:35 -08:00
Nathan Hartman
d82cc3ccc6 arch/stm32f7: Fix nxstyle errors
arch/arm/src/stm32f7/chip.h,
arch/arm/src/stm32f7/stm32_adc.h,
arch/arm/src/stm32f7/stm32_allocateheap.c,
arch/arm/src/stm32f7/stm32_bbsram.h,
arch/arm/src/stm32f7/stm32_can.h,
arch/arm/src/stm32f7/stm32_capture.c,
arch/arm/src/stm32f7/stm32_capture.h:

    * Fix nxstyle errors.
2021-01-31 19:55:34 +00:00
Alan C. Assis
b0d611d3dc Replace ARM_LWL_CONSOLE with generic LWL_CONSOLE 2021-01-31 06:14:50 -08:00
Masayuki Ishikawa
5bcdeb0851 arch: imx6: Fix a compile error with CONFIG_DEBUG_ASSERTIONS=y
Summary:
- This commit fixes a compile error in imx_enet.c
  with CONFIG_DEBUG_ASSERTIONS=y

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-01-29 12:09:47 -03:00
Masayuki Ishikawa
585884fde9 arch: imx6: Add CONFIG_IMX_ENET_NTXBUFFERS check in imx_enet.c
Summary:
- This commit checks CONFIG_IMX_ENET_NTXBUFFERS without
  CONFIG_NET_TCP_WRITE_BUFFERS

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-01-29 00:05:01 -08:00
Masayuki Ishikawa
6140969f16 arch: imx6: Fix imx_enet.c if CONFIG_IMX_ENET_NTXBUFFERS=1
Summary:
- This commit fixes imx_enet.c if CONFIG_IMX_ENET_NTXBUFFERS=1
- Also adds some ninfo() debug messages

Impact:
- imx_enet.c only

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-01-28 18:41:34 -08:00
Masayuki Ishikawa
977367ce04 arch: imx6: Apply the latest imxrt/imxrt_enet.c to imx6/imx_enet.c
Summary:
- Since imx_enet.c is based on imxrt_enet.c and still under debugging,
  the differences should be minimum to keep tracking the changes

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-01-27 22:58:29 -08:00
Matias N
e5200d4af9 nrf52: add stackcheck support 2021-01-27 09:49:16 -08:00
baggio63446333
7723ce46ce arch: cxd56xx: Add I2C bitbang lower driver
Add I2C bitbang lower driver for cxd56xx.
2021-01-26 13:59:30 -03:00
Matias N
d2f9544556 nRF52 GPIO: tiny optimization, do not decode PORT when no PORT1 2021-01-24 19:03:56 -08:00
Matias N
28caf27229 nRF52: add I2C bitbang implementation 2021-01-24 19:03:56 -08:00
Alin Jerpelea
56ef94086f arch: arm: cxd56xx: update license to Apache 2.0
This is a license change to Apache 2.0 license.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-01-25 09:09:30 +09:00
Xiang Xiao
94da3e4c3a arch: Remove critical section inside up_schedule_sigaction
since nxsig_tcbdispatch already hold it for us

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I2fe6ad840bdca3ec0eaa76a9af3b6929c7d5a721
2021-01-22 08:34:07 +01:00
David Sidrane
a2f82542ef stm32f412:Replaced Kludged pinmap with one for SoC.
The stm32f412 was not a clean port. This is one step to fix
   it. The shortcuts taken has caused more wasted hours finding
   bad pin mappings then doing the job correctlry to begin with.

   stm32:Kconfig Add CAN2 on STM32F412
2021-01-21 06:56:33 -08:00
Matias N
ed5e494298 nRF52: FIX wrong bitmask for DRIVE setting
This bug made certain values of DRIVE setting
to be wrongly applied (which can be dangerous
under certain situations since for example H0D1
was mapped to H0H1).
2021-01-21 00:36:56 -08:00
Matias N
5fc34a6e8c nRF52: support stack coloration 2021-01-18 17:29:36 -03:00
Nathan Hartman
3620728db2 arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_dtcm.c:
arch/arm/src/stm32h7/stm32_lowputc.c:

    * Fix nxstyle issues.
2021-01-18 17:28:05 -03:00
Brennan Ashton
b6fbcb649c nrf52: Add a static copy buffer for i2c
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2021-01-18 00:45:59 -08:00
Brennan Ashton
3a64783273 nrf52: Add simple i2c test configuration
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
2021-01-17 23:46:01 -08:00
raiden00pl
0f1c026a16 nrf52_i2c: add support for I2C_M_NOSTART flags 2021-01-17 13:39:28 -08:00
Nathan Hartman
df8139c59b arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_rtc.c:
arch/arm/src/stm32h7/stm32_rtc.h:

    * Fix nxstyle issues.
2021-01-17 09:52:17 -08:00
Matias N
93ef2e7174 nrf52 GPIO: set GPIO drive setting and missing input buffer configuration 2021-01-16 21:04:44 -08:00
Matias N
2fcfd63f8e nrf52: fix build without serial 2021-01-16 21:04:44 -08:00
Matias N
6f3f1c07fb nrf52 i2c: disable peripheral while configuring 2021-01-16 21:04:44 -08:00
Matias N
e1b3374bce nrf52 spi: build fixes and a missing register setting (polarity) 2021-01-16 21:04:44 -08:00
Matias N
ebe596bcd1 nrf52: enable and fix build for SPI BITORDER 2021-01-16 21:04:44 -08:00
Matias N
5d4463121f nrf52: fix SPI3 irq macro naming 2021-01-16 21:04:44 -08:00
Matias N
c526f01ba7 nrf52: fix build for PWM without multichan enabled 2021-01-16 21:04:44 -08:00
Masayuki Ishikawa
497e2f9e0c arch: tiva: Fix lm3s_ethernet.c with DEBUGASSERT
Summary:
- This commit fixes DEBUGASSERT in lm3s_ethernet.c

Impact:
- lm3s_ethernet.c only

Testing:
- Tested with lm3s6965-ek:discover with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-01-16 10:40:17 +01:00
Nathan Hartman
75d3ae959f arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_sdmmc.h:

    * Fix nxstyle issues.
2021-01-15 23:23:08 +01:00
Nathan Hartman
fda9f63bd8 arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_tim.c:

    * Fix nxstyle issues.
2021-01-15 23:23:08 +01:00
Nathan Hartman
c76fd28b83 arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_uid.c:

    * Fix nxstyle issues.
2021-01-15 23:23:08 +01:00
Nathan Hartman
07b1014ef0 arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_usbhost.h:

    * Fix nxstyle issues.
2021-01-15 23:23:08 +01:00
Nathan Hartman
938db2fa9e arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_userspace.c:
arch/arm/src/stm32h7/stm32_userspace.h:

    * Fix nxstyle issues.
2021-01-15 23:23:08 +01:00
Masayuki Ishikawa
5f0e334974 arch: cxd56xx: Fix a compile warning with CONFIG_DEBUG_ERROR=y
Summary:
- This commit fixes a compile warning in cxd56_sdhci.c

Impact:
- None

Testing:
- Built with spresense:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-01-14 20:48:25 -06:00
David Sidrane
657088318a stm32412: Fixes pinmap CAN1 2021-01-13 11:01:44 -06:00
Nathan Hartman
095d99717b arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_rcc.c:
arch/arm/src/stm32h7/stm32_rcc.h:

    * Fix nxstyle issues.
2021-01-13 11:01:03 -06:00
Xiang Xiao
0dc6990166 Fix nxstyle warning
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-01-13 08:57:58 +01:00
Xiang Xiao
0536953ded Kernel module should prefer functions with nx/kmm prefix
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-01-13 08:57:58 +01:00
Nathan Hartman
15480e51cf arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_qencoder.c:

    * Fix nxstyle issues.
2021-01-12 19:06:44 +01:00
Nathan Hartman
2cfbfa8213 arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_pwr.c:

    * Fix nxstyle issues.
2021-01-07 01:11:43 +01:00
Nathan Hartman
f30097d0ab arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_pmstop.c:

    * Fix nxstyle issues.
2021-01-07 01:11:43 +01:00
Nathan Hartman
4c82459851 arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_dma.h:

    * Fix nxstyle issues.
2021-01-07 01:11:43 +01:00
Nathan Hartman
8cc9308da7 arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/chip.h:

    * Fix nxstyle issues.
2021-01-07 01:11:43 +01:00
ligd
f63db66382 mqueue: add file_mq_xx for kernel use
Change-Id: Ida12f5938388cca2f233a4cde90277a218033645
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-01-05 02:40:43 -06:00
Nathan Hartman
4ccaedf91f arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_adc.c:
arch/arm/src/stm32h7/stm32_adc.h:

    * Fix nxstyle issues.
2021-01-04 13:04:51 -06:00
Nathan Hartman
ec0b2f063c arch/stm32h7: Fix nxstyle errors
arch/arm/src/stm32h7/stm32_bbsram.h:

    * Fix nxstyle issues.
2021-01-03 20:30:45 -06:00
Nathan Hartman
7592fc17d3 arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/stm32_otghs.h:

    * Fix nxstyle issues.
2021-01-01 18:17:03 +01:00
Nathan Hartman
588227ed7b arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/stm32_otgfs.h:

    * Fix nxstyle issues.
2020-12-31 20:32:13 +01:00
Xiang Xiao
c647faa117 Fix nxstyle warning
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-31 09:37:29 +01:00
Xiang Xiao
0defe43282 OS internal function should indicate the error by return negative value
instead to change errno value by calling set_errno

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-31 09:37:29 +01:00
Nathan Hartman
81224cc596 arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/stm32_spi.h:

    * Fix nxstyle issues.
2020-12-30 10:20:15 -06:00
Nathan Hartman
763aae8155 arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/stm32_rtc.h:

    * Fix nxstyle issues.
2020-12-29 08:36:31 -06:00
Peter van der Perk
673a4b5b39 arch: S32K/Kinetis: Fix RTC settime prescaler 2020-12-28 23:32:33 +01:00
Masayuki Ishikawa
b784fd6c3c arch: cxd56xx: Replace license header with Apache License 2.0
Summary:
- This commit replaces SHES related headers under cxd56xx

Impact:
- No impact

Testing:
- Build check only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2020-12-28 08:43:35 +01:00
Nathan Hartman
080b2dfceb arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/stm32_exti.h:
arch/arm/src/stm32/stm32_flash.c:
arch/arm/src/stm32/stm32_fsmc.c:
arch/arm/src/stm32/stm32_fsmc.h:
arch/arm/src/stm32/stm32_hciuart.h:
arch/arm/src/stm32/stm32_mpuinit.h:
arch/arm/src/stm32/stm32_rtc.c:

    * Fix nxstyle issues.
2020-12-24 23:21:16 +01:00