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Author SHA1 Message Date
Jiuzhu Dong
48493dac5b telnet: fix crash about telnet client connect 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-03-05 06:55:17 +09:00
Gustavo Henrique Nihei
1aebe47c71 xtensa/esp32: Use OR operation when configuring pin driver 2021-03-04 16:36:48 +00:00
Gustavo Henrique Nihei
23f0d8c17b xtensa/esp32: Fix default GPIO function when no option is provided 2021-03-04 16:36:48 +00:00
Gustavo Henrique Nihei
9c366aad94 xtensa/esp32: Allow pin to be configured as Input and Output simultaneously 2021-03-04 16:36:48 +00:00
Gustavo Henrique Nihei
210a77de93 xtensa/esp32: Configure GPIO as INPUT only when required 2021-03-04 16:36:48 +00:00
Gustavo Henrique Nihei
37ac70b7d9 xtensa/esp32: Add configuration for testing BMP180 2021-03-04 16:31:51 +00:00
Gustavo Henrique Nihei
0735e8c2a7 xtensa/esp32: Fix BMP180 erroneously depending on I2C_DRIVER 2021-03-04 16:31:51 +00:00
Gustavo Henrique Nihei
fa36897541 risc-v/esp32c3: Fix Kconfig file formatting 2021-03-04 16:31:51 +00:00
Gustavo Henrique Nihei
f5342d00fc xtensa/esp32: Fix Kconfig file formatting 2021-03-04 16:31:51 +00:00
Gustavo Henrique Nihei
984e0f0ec9 xtensa/esp32: Add missing option for I2C reset 2021-03-04 16:31:51 +00:00
Gustavo Henrique Nihei
79ea96a1d0 xtensa/esp32: Fix ESP32_I2C option bringing the char driver 2021-03-04 16:31:51 +00:00
ligd
d2488715c0 fs/mount: fix mount cmd break out when meet stat error 
Change-Id: I9307fe67837a6519fffa1844fcfd794f735d2fdd
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-04 07:11:51 -08:00
ligd
48d49e5a7c mqueue: add poll support 
Change-Id: I7e908f6a6c00158c0946587dd79ae3dc5d279d37
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-04 07:11:43 -08:00
David Sidrane
8b73e30185 arch/arm/src/stm32h7/Kconfig 
stm32h7:lse fix Kconfig help text
 2021-03-04 07:10:18 -08:00
Alan C. Assis
29af35faef esp32: Add board config to support MCP2515 2021-03-04 14:57:56 +00:00
David Sidrane
296d94b5cb stm32f7:lse Use Kconfig values directly 2021-03-04 00:16:10 -08:00
Masayuki Ishikawa
d412819160 Revert "libs: misc: Remove critical section in lib_filesem.c for SMP" 
This reverts commit 191ada2296.
 2021-03-03 22:34:07 -08:00
ligd
0d24582fe0 syslog_rpmsg: fix system crash when open CONFIG_SCHED_HAVE_PARENT 
Reason:
nx_start use syslog at every early time event the idle thread not
full setup, then syslog_rpmsg -> work_queue -> work_signal ->
nxsig_kill -> rtcb is NULL -> crash

Fix:
sched work_queue after is_rpmsg_ept_ready() is true

Change-Id: I225469ff2526e4b810bf3e23473b55d57e64a1ff
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-03 19:08:15 -08:00
ligd
d009074ed5 sim/up_uart.c: fix losting uart data when user paste long cmd 
N/A

Change-Id: I66c01c0789fc83ae8f6db522d61ff8ab63cd9211
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-03 19:05:22 -08:00
Fotis Panagiotopoulos
f423403dfa stm32_wwdg debug log formatting 2021-03-03 19:02:04 -08:00
Jiuzhu Dong
3c0354aba6 net/socket: delete config CONFIG_NSOCKET_DESCRIPTORS 
N/A

Change-Id: I7d10ec460c351e4fbcdc19b3a8284dcb77073722
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-03-03 19:01:41 -08:00
Jiuzhu Dong
4d5a964f29 net: unify socket into file descriptor 
Change-Id: I9bcd21564e6c97d3edbb38aed1748c114160ea36
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-03-03 19:01:41 -08:00
Gustavo Henrique Nihei
5e9e2bec32 xtensa/esp32: Change I2C SCL default pin to a valid one 
Current default pin for I2C SCL is not available for mapping with IOMUX
peripheral.
 2021-03-03 19:00:15 -08:00
Alin Jerpelea
d6b50a1d3f libs: nxstyle fixes 
nxstyle fixes to pass the CI checks

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-03 18:52:53 -08:00
Alin Jerpelea
796ef13b20 tools: nxstyle: add L_tmpnam/P_tmpdir exceptions 
Those exceptions are defined in
https://pubs.opengroup.org/onlinepubs/9699919799/functions/tempnam.html

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-03 18:52:53 -08:00
Alin Jerpelea
b5d4a01821 libs: Author Gregory Nutt: update licenses to Apache 
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-03 18:52:53 -08:00
Nathan Hartman
3ac61053ce arch/stm32, arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32/hardware/stm32_dma2d.h,
arch/arm/src/stm32/hardware/stm32_ltdc.h,
arch/arm/src/stm32/stm32_dma2d.c,
arch/arm/src/stm32/stm32_ltdc.c,
arch/arm/src/stm32f7/hardware/stm32_dma2d.h,
arch/arm/src/stm32f7/hardware/stm32_ltdc.h,
arch/arm/src/stm32f7/stm32_dma2d.c, and
arch/arm/src/stm32f7/stm32_ltdc.c:

    * Fix nxstyle "mixed case identifier" errors for the
      following identifiers:

      DMA2D_xGPFCCR_ALPHA         -> DMA2D_XGPFCCR_ALPHA
      DMA2D_xGPFCCR_AM            -> DMA2D_XGPFCCR_AM
      DMA2D_xGPFCCR_CCM           -> DMA2D_XGPFCCR_CCM
      DMA2D_xGPFCCR_CM            -> DMA2D_XGPFCCR_CM
      DMA2D_xGPFCCR_CS            -> DMA2D_XGPFCCR_CS
      DMA2D_xGPFCCR_START         -> DMA2D_XGPFCCR_START
      LTDC_LxBFCR_BF1             -> LTDC_LXBFCR_BF1
      LTDC_LxBFCR_BF2             -> LTDC_LXBFCR_BF2
      LTDC_LxCFBLR_CFBLL          -> LTDC_LXCFBLR_CFBLL
      LTDC_LxCFBLR_CFBP           -> LTDC_LXCFBLR_CFBP
      LTDC_LxCR_CLUTEN            -> LTDC_LXCR_CLUTEN
      LTDC_LxCR_COLKEN            -> LTDC_LXCR_COLKEN
      LTDC_LxCR_LEN               -> LTDC_LXCR_LEN
      LTDC_LxWHPCR_WHSPPOS        -> LTDC_LXWHPCR_WHSPPOS
      LTDC_LxWHPCR_WHSTPOS        -> LTDC_LXWHPCR_WHSTPOS
      LTDC_LxWVPCR_WVSPPOS        -> LTDC_LXWVPCR_WVSPPOS
      LTDC_LxWVPCR_WVSTPOS        -> LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_LxWHPCR_WHSTPOS  -> STM32_LTDC_LXWHPCR_WHSTPOS
      STM32_LTDC_LxWVPCR_WVSTPOS  -> STM32_LTDC_LXWVPCR_WVSTPOS
      STM32_LTDC_Lx_BYPP          -> STM32_LTDC_LX_BYPP
      DMA2D_xGCOLR_BLUE           -> DMA2D_XGCOLR_BLUE
      DMA2D_xGCOLR_BLUE_MASK      -> DMA2D_XGCOLR_BLUE_MASK
      DMA2D_xGCOLR_BLUE_SHIFT     -> DMA2D_XGCOLR_BLUE_SHIFT
      DMA2D_xGCOLR_GREEN          -> DMA2D_XGCOLR_GREEN
      DMA2D_xGCOLR_GREEN_MASK     -> DMA2D_XGCOLR_GREEN_MASK
      DMA2D_xGCOLR_GREEN_SHIFT    -> DMA2D_XGCOLR_GREEN_SHIFT
      DMA2D_xGCOLR_RED            -> DMA2D_XGCOLR_RED
      DMA2D_xGCOLR_RED_MASK       -> DMA2D_XGCOLR_RED_MASK
      DMA2D_xGCOLR_RED_SHIFT      -> DMA2D_XGCOLR_RED_SHIFT
      DMA2D_xGOR                  -> DMA2D_XGOR
      DMA2D_xGOR_MASK             -> DMA2D_XGOR_MASK
      DMA2D_xGOR_SHIFT            -> DMA2D_XGOR_SHIFT
      DMA2D_xGPFCCR_ALPHA_MASK    -> DMA2D_XGPFCCR_ALPHA_MASK
      DMA2D_xGPFCCR_ALPHA_SHIFT   -> DMA2D_XGPFCCR_ALPHA_SHIFT
      DMA2D_xGPFCCR_AM_MASK       -> DMA2D_XGPFCCR_AM_MASK
      DMA2D_xGPFCCR_AM_SHIFT      -> DMA2D_XGPFCCR_AM_SHIFT
      DMA2D_xGPFCCR_CM_MASK       -> DMA2D_XGPFCCR_CM_MASK
      DMA2D_xGPFCCR_CM_SHIFT      -> DMA2D_XGPFCCR_CM_SHIFT
      DMA2D_xGPFCCR_CS_MASK       -> DMA2D_XGPFCCR_CS_MASK
      DMA2D_xGPFCCR_CS_SHIFT      -> DMA2D_XGPFCCR_CS_SHIFT
      LTDC_LxBFCR_BF1_MASK        -> LTDC_LXBFCR_BF1_MASK
      LTDC_LxBFCR_BF1_SHIFT       -> LTDC_LXBFCR_BF1_SHIFT
      LTDC_LxBFCR_BF2_MASK        -> LTDC_LXBFCR_BF2_MASK
      LTDC_LxBFCR_BF2_SHIFT       -> LTDC_LXBFCR_BF2_SHIFT
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA          -> LTDC_LXCACR_CONSTA
      LTDC_LxCACR_CONSTA_MASK     -> LTDC_LXCACR_CONSTA_MASK
      LTDC_LxCACR_CONSTA_SHIFT    -> LTDC_LXCACR_CONSTA_SHIFT
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN            -> LTDC_LXCFBLNR_LN
      LTDC_LxCFBLNR_LN_MASK       -> LTDC_LXCFBLNR_LN_MASK
      LTDC_LxCFBLNR_LN_SHIFT      -> LTDC_LXCFBLNR_LN_SHIFT
      LTDC_LxCFBLR_CFBLL_MASK     -> LTDC_LXCFBLR_CFBLL_MASK
      LTDC_LxCFBLR_CFBLL_SHIFT    -> LTDC_LXCFBLR_CFBLL_SHIFT
      LTDC_LxCFBLR_CFBP_MASK      -> LTDC_LXCFBLR_CFBP_MASK
      LTDC_LxCFBLR_CFBP_SHIFT     -> LTDC_LXCFBLR_CFBP_SHIFT
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE          -> LTDC_LXCKCR_CKBLUE
      LTDC_LxCKCR_CKBLUE_MASK     -> LTDC_LXCKCR_CKBLUE_MASK
      LTDC_LxCKCR_CKBLUE_SHIFT    -> LTDC_LXCKCR_CKBLUE_SHIFT
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN         -> LTDC_LXCKCR_CKGREEN
      LTDC_LxCKCR_CKGREEN_MASK    -> LTDC_LXCKCR_CKGREEN_MASK
      LTDC_LxCKCR_CKGREEN_SHIFT   -> LTDC_LXCKCR_CKGREEN_SHIFT
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED           -> LTDC_LXCKCR_CKRED
      LTDC_LxCKCR_CKRED_MASK      -> LTDC_LXCKCR_CKRED_MASK
      LTDC_LxCKCR_CKRED_SHIFT     -> LTDC_LXCKCR_CKRED_SHIFT
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE          -> LTDC_LXCLUTWR_BLUE
      LTDC_LxCLUTWR_BLUE_MASK     -> LTDC_LXCLUTWR_BLUE_MASK
      LTDC_LxCLUTWR_BLUE_SHIFT    -> LTDC_LXCLUTWR_BLUE_SHIFT
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD       -> LTDC_LXCLUTWR_CLUTADD
      LTDC_LxCLUTWR_CLUTADD_MASK  -> LTDC_LXCLUTWR_CLUTADD_MASK
      LTDC_LxCLUTWR_CLUTADD_SHIFT -> LTDC_LXCLUTWR_CLUTADD_SHIFT
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN         -> LTDC_LXCLUTWR_GREEN
      LTDC_LxCLUTWR_GREEN_MASK    -> LTDC_LXCLUTWR_GREEN_MASK
      LTDC_LxCLUTWR_GREEN_SHIFT   -> LTDC_LXCLUTWR_GREEN_SHIFT
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED           -> LTDC_LXCLUTWR_RED
      LTDC_LxCLUTWR_RED_MASK      -> LTDC_LXCLUTWR_RED_MASK
      LTDC_LxCLUTWR_RED_SHIFT     -> LTDC_LXCLUTWR_RED_SHIFT
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA         -> LTDC_LXDCCR_DCALPHA
      LTDC_LxDCCR_DCALPHA_MASK    -> LTDC_LXDCCR_DCALPHA_MASK
      LTDC_LxDCCR_DCALPHA_SHIFT   -> LTDC_LXDCCR_DCALPHA_SHIFT
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE          -> LTDC_LXDCCR_DCBLUE
      LTDC_LxDCCR_DCBLUE_MASK     -> LTDC_LXDCCR_DCBLUE_MASK
      LTDC_LxDCCR_DCBLUE_SHIFT    -> LTDC_LXDCCR_DCBLUE_SHIFT
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN         -> LTDC_LXDCCR_DCGREEN
      LTDC_LxDCCR_DCGREEN_MASK    -> LTDC_LXDCCR_DCGREEN_MASK
      LTDC_LxDCCR_DCGREEN_SHIFT   -> LTDC_LXDCCR_DCGREEN_SHIFT
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED           -> LTDC_LXDCCR_DCRED
      LTDC_LxDCCR_DCRED_MASK      -> LTDC_LXDCCR_DCRED_MASK
      LTDC_LxDCCR_DCRED_SHIFT     -> LTDC_LXDCCR_DCRED_SHIFT
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF              -> LTDC_LXPFCR_PF
      LTDC_LxPFCR_PF_MASK         -> LTDC_LXPFCR_PF_MASK
      LTDC_LxPFCR_PF_SHIFT        -> LTDC_LXPFCR_PF_SHIFT
      LTDC_LxWHPCR_WHSPPOS_MASK   -> LTDC_LXWHPCR_WHSPPOS_MASK
      LTDC_LxWHPCR_WHSPPOS_SHIFT  -> LTDC_LXWHPCR_WHSPPOS_SHIFT
      LTDC_LxWHPCR_WHSTPOS_MASK   -> LTDC_LXWHPCR_WHSTPOS_MASK
      LTDC_LxWHPCR_WHSTPOS_SHIFT  -> LTDC_LXWHPCR_WHSTPOS_SHIFT
      LTDC_LxWVPCR_WVSPPOS_MASK   -> LTDC_LXWVPCR_WVSPPOS_MASK
      LTDC_LxWVPCR_WVSPPOS_SHIFT  -> LTDC_LXWVPCR_WVSPPOS_SHIFT
      LTDC_LxWVPCR_WVSTPOS_MASK   -> LTDC_LXWVPCR_WVSTPOS_MASK
      LTDC_LxWVPCR_WVSTPOS_SHIFT  -> LTDC_LXWVPCR_WVSTPOS_SHIFT

    * Fix all other nxstyle errors in the affected files.
 2021-03-03 18:49:20 -08:00
Gustavo Henrique Nihei
b1b4190802 risc-v/esp32c3: Fix default GPIO function when no option is provided 2021-03-03 18:46:43 -08:00
Gustavo Henrique Nihei
bc335009d9 risc-v/esp32c3: Allow pin to be configured as Input and Output simultaneously 2021-03-03 18:46:43 -08:00
Abdelatif Guettouche
85620c3c1a risc-v/esp32c3: Add more flash options to esptool. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-03 18:28:18 -08:00
Abdelatif Guettouche
77302f9d3a xtensa/esp32: Add more flash options to esptool. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-03-03 18:28:18 -08:00
Xiang Xiao
c8d4a4c76a mtd/progmem: Add up_progmem_read callback guarded by ARCH_HAVE_PROGMEM_READ 
since sometime platform code need do some special action during memcpy

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id108ef4232376feab3e37e9b3aee9a7927a03bd4
 2021-03-03 13:47:59 -08:00
Xiang Xiao
0aa78ccc81 mtd/progmem: Let MTD_PROGMEM depend on ARCH_HAVE_PROGMEM 
and remove the reference of CONFIG_ARCH_HAVE_PROGMEM from code

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I89a73f138d54718ee8bc9345958675d7a2a34ba8
 2021-03-03 13:47:59 -08:00
ligd
f9d20ea4d2 sigdeliver: fix system block when kill signal to idle in SMP 
Bug description:

CONFIG_SMP=y

Suppose we have 2 cores in SMP, here is the ps return:

PID GROUP CPU PRI POLICY TYPE    NPX STATE     STACK   USED  FILLED COMMAND
  0     0   0   0 FIFO   Kthread N-- Assigned 004076 000748  18.3%  CPU0 IDLE
  1     0   1   0 FIFO   Kthread N-- Running  004096 000540  13.1%  CPU1 IDLE

nsh> kill -4 0
or:
nsh> kill -4 1

system blocked.

Reason:

In func xx_sigdeliver() restore stage, when saved_irqcount == 0, that means
rtcb NOT in critical_section before switch to xx_sigdeliver(), then we need
reset the critical_section state before swith back.

Fix:

Add condition to cover saved_irqcount == 0.

Change-Id: I4af7f95e47f6d78a4094c3757d39b01ac9d533b3
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-03 15:03:32 +00:00
ligd
a27fe37120 signal/sig_kill.c: remove the limitation of kill(0, xx) 
since there are situation which send singal to idle thread already,

CONFIG_SCHED_CHILD_STATUS=y
CONFIG_SCHED_HAVE_PARENT=y

Signo SIGCHLD will send to parent group, when child exit

Change-Id: Iceb2ac41948c1c3418839a3b5de70985d48c75d1
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2021-03-03 15:03:32 +00:00
Yuichi Nakamura
81d917f741 boards/raspberrypi-pico: Add new config ssd1306 2021-03-03 09:35:45 -03:00
Yuichi Nakamura
599e5b1bb2 boards/raspberrypi-pico: Fix board settings to support i2c and ssd1306 2021-03-03 09:35:45 -03:00
Yuichi Nakamura
9d0b3594f6 arm/rp2040: Add RP2040 I2C device support 2021-03-03 09:35:45 -03:00
Yuichi Nakamura
60b18467f3 arm/rp2040: Add rp2040_gpio_set_pulls() 2021-03-03 09:35:45 -03:00
Xiang Xiao
8d0fd4038b Remove the empty xxx_initialize functions 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I63cb6b37f78e910663724659e11f53e3335d419f
 2021-03-03 08:21:04 +00:00
David Sidrane
ab5f46d46c stm32h7:Add DBGMCU 2021-03-02 18:28:19 -08:00
Alin Jerpelea
41b029876f pcm_decode: add RAW format support 
adds CONFIG_AUDIO_FORMAT_RAW as an option to the PCM
audio format for devices expecting raw data without
a header.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-03-02 18:27:45 -08:00
chenwen
19627095e4 esp32/esp32_allocateheap.c: Support the maximum available internal heap configuration 2021-03-02 18:27:20 -08:00
chenwen
516c553b97 esp32/esp32_wifi_adapter.c: Fix the issue of WiFi internal malloc from PSRAM 2021-03-02 18:27:20 -08:00
Nathan Hartman
a3f0923ad0 arch/stm32f7: Fix nxstyle errors 
arch/arm/src/stm32f7/stm32_tim.h:

    * Fix nxstyle errors.
 2021-03-02 21:34:33 +00:00
David Sidrane
1e5754232a stm32f7:Add option to auto select LSE CAPABILITY 
This Knob will cycle through the values from
   low to high. To avoid damaging the crystal.
   We want to use the lowest setting that gets
   the OSC running. See app note AN2867
 2021-03-02 14:34:56 -03:00
David Sidrane
9fbd7f9dc5 stm32h7:Add option to auto select LSE CAPABILITY 
This Knob will cycle through the correct*
   values from low to high. To avoid damaging
   the crystal. We want to use the lowest setting
   that gets the OSC running. See app note AN2867

    *It will take into account the rev of the silicon
    and use the correct code points to achive the drive
    strength. See Eratta ES0392 Rev 7 2.2.14 LSE oscillator
    driving capability selection bits are swapped.
 2021-03-02 14:34:56 -03:00
Masayuki Ishikawa
9d370fc363 sched: task: Call nxtask_flushstreams() without critical section 
Summary:
- During investigating critical section with semaphores, I noticed
  that nxtask_flushstreams() is called with a critical section.
- The function calls lib_flushall() which handles a semaphore
  in userspace.
- So it should be done without a critical section

Impact:
- SMP only

Testing:
- Tested with ostest the following configs
- esp32-devkitc:smp (QEMU), sabre-6quad:smp (QEMU)
- maix-bit:smp (QEMU), sim:smp
- spresense:smp
- Tested with nxplayer and stress test with spresense:wifi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-03-02 05:05:29 -08:00
Michael Jung
cbe3fb5c60 libs/libc: License Clearance 
Change the copyright header of assorted source files in libs/libc to the
ASF version.  I was listed as the author in these files.  I did also
check the heritage of those files and besides me they have only been
changed by the following people, all of whom did sign a CLA to the best
of my knowledge:

Alin Jerpelea
Haitao Liu
Gregory Nutt
Yamamoto Takashi
Xiang Xiao

Signed-off-by: Michael Jung <mijung@gmx.net>
 2021-03-02 03:44:06 -08:00
Michael Jung
fbfddda28b armv8-m: Fix EXC_RETURN for non-secure usage 
With TrustZone support in armv8-m the bit-fields in EXC_RETURN have been
extended.  Bit 6 ('S') now specifies whether the interrupted program was
running in the Non-Secure (S=0) or Secure (S=1) security state.
Furthermore, Bit 0 ('ES' - Exception Secure) specifies the
security state athe exception is taken to (0: Non-Secure, 1: Secure).

When NuttX is run together with TrustedFirmware-M as the application in
the non-secure world both the S and the ES bits have to be set to '0'.
For armv8-m those are also the correct values if TrustZone is not
implemented on the respective MCU or if it is disabled.

Signed-off-by: Michael Jung <mijung@gmx.net>
 2021-03-02 07:28:42 -03:00