Commit Graph

20793 Commits

Author SHA1 Message Date
Mingjie Shen
49afeb4d63 arch/arm/stm: Fix duplicate include guard
The following macros
  __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_FLASH_H
  __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H
are used in other header files.

Signed-off-by: Mingjie Shen <shen497@purdue.edu>
2023-06-25 12:23:23 +03:00
Lucas Saavedra Vaz
8aeba210e4 arch/risc-v/espressif: Add full GPIO support
Full GPIO support using Espressif's HAL
2023-06-24 13:11:45 +08:00
Stuart Ianna
2db6ea9984 litex/gpio: Fix incorrect declaration name. 2023-06-23 12:29:59 +08:00
Xiang Xiao
0eeca0f375 build: Replace "$(shell $(INCDIR) $(CC) ...)" with $(INCDIR_PREFIX)
to unify the way to get include directories

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-23 00:11:25 +03:00
anjiahao
4ae17a6f7b sched:Automatically find deadlocks when assert
When asserting, automatically analyze whether
there is a deadlock in the thread, and if there
is a deadlock, print out the deadlocked thread.

The principle is to analyze whether there is
a lock ring through the tcb holder.

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-06-22 16:08:03 +08:00
simbit18
f0a74eb492 Fix Kconfig style
Remove spaces from Kconfig files
2023-06-22 11:46:09 +09:00
simbit18
f930b4f6f5 Fix Kconfig style
Remove TABs from Kconfig files
Replace help => ---help---
Add comments
2023-06-20 12:54:50 -03:00
Masayuki Ishikawa
c5641b0252 Revert "riscv/swint: Give the full tcb to the context switch routine"
This reverts commit 040eb3c990.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
2c6ad5c2bf Revert "riscv/fpu: Restore correct lazy-FPU functionality"
This reverts commit 35c27b5a9a.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
9d84d79b29 Revert "riscv/saveusercontext: Fix FPU state save"
This reverts commit 669196910c.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
0124533cc3 Revert "riscv/addrenv: Move addrenv_switch() to correct place after FPU change"
This reverts commit da319bbd85.
2023-06-20 06:17:11 +09:00
Masayuki Ishikawa
7410f4a6b8 Revert "riscv/lazyfpu: Add option to disable lazy FPU"
This reverts commit 425cc89989.
2023-06-20 06:17:11 +09:00
simbit18
3f4151525d Fix Kconfig style
Remove TABs from Kconfig files
Add comments
2023-06-19 20:05:57 +03:00
Ville Juven
425cc89989 riscv/lazyfpu: Add option to disable lazy FPU
Adds option to use the old implementation where FPU is stored into
the process stack.
2023-06-19 19:28:07 +08:00
Ville Juven
da319bbd85 riscv/addrenv: Move addrenv_switch() to correct place after FPU change
The new address environment must be instantiated prior to restoring FPU
state as the CPU status register is in tcb->regs, which is user stack.
2023-06-19 19:28:07 +08:00
Ville Juven
669196910c riscv/saveusercontext: Fix FPU state save 2023-06-19 19:28:07 +08:00
Ville Juven
35c27b5a9a riscv/fpu: Restore correct lazy-FPU functionality
- Save the FPU registers into the tcb so they don't get lost if the stack
  frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
  - Save ONLY if FPU is dirty
  - Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
2023-06-19 19:28:07 +08:00
Ville Juven
040eb3c990 riscv/swint: Give the full tcb to the context switch routine
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.

Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
2023-06-19 19:28:07 +08:00
Eero Nurkkala
4494e75e87 risc-v/mpfs: add CoreMMC support
This adds support for the CoreMMC v3.1 FPGA driver as described
in Microchip Handbook HB0510. The driver doesn't support DMA.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-06-19 19:24:51 +08:00
Xiang Xiao
ddbe9eb6ab mm: Rename mm_memdump_s to malltask
align with the naming of mallinfo_task

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-18 09:12:14 +03:00
Richard Tucker
225d347306 stm32 tickless: stop assertion when calling up_timer_gettime before initialised
up_timer_gettime can be called before module is initialised when
CONFIG_SCHED_IRQMONITOR is enabled.

This fix aligns with stm32f7 implementation.
2023-06-17 11:05:40 -03:00
Dong Heng
8f25329260 xtensa/esp32s3: SPI support quad I/O mode 2023-06-16 16:07:05 -03:00
Tiago Medicci Serrano
17c65d2067 risc-v/espressif: use the unquoted CHIP_SERIES variable
Instead of using `CONFIG_ESPRESSIF_CHIP_SERIES`, use the unquoted
version `CHIP_SERIES`.
2023-06-16 11:14:36 +08:00
Tiago Medicci Serrano
368b6cb489 esp32s3/wifi: update Wi-Fi driver to the newest esp-hal-3rdparty 2023-06-16 11:14:36 +08:00
Tiago Medicci Serrano
6559ac4034 risc-v/espressif: update to the newest esp-hal-3rdparty version
Also, get esp-hal-3rdparty by git cloning (instead of downloaded)
to enable getting its git submodules.
2023-06-16 11:14:36 +08:00
Dong Heng
d492823128 xtensa/esp32s3: Add USB OTG device driver 2023-06-14 18:04:27 -03:00
Lucas Saavedra Vaz
4bcf454ae5 arch/xtensa/esp32s2: Fix SPI DMA implementation 2023-06-15 03:29:30 +08:00
raiden00pl
2f58b55b4d arch/{nrf52|nrf53}/usbd: various fixes to improve USB stability
USBD has many limitation that make it hard to work properly:
- only one EasyDMA channel which must be shared for all EPs
- only one DMA transfer can take place at a time
- some registers are unavailable during DMA transfer
- in case of any problems, the peripheral silently blocks,
  or lose the transmitted bytes without information for the user

This commit is trying to fix these problem and makes the USBS stack more reliable.

Tested with high-speed CDCACM data transfers and that's the best I've been able to get in terms of stability.
2023-06-14 16:23:25 -03:00
Ville Juven
9b5746cb5f riscv/barrier: Define more granular memory barriers
Separate barriers for full (memory + I/O) and local memory (cache) flushing.
2023-06-14 16:14:57 -03:00
Zhe Weng
f2690837e7 arch/sim: Support more sockopts on native socket
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-06-14 15:50:31 +03:00
SPRESENSE
b1f3d5e573 arm/cxd56xx: Fix build error in CONFIG_PM=y 2023-06-14 08:49:19 +02:00
Huang Qi
84f4cf9b9d riscv/vfork: Replace jal with call for long jump
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-06-14 02:01:04 +08:00
zhanghongyu
272e62018a sim/posix/sim_hostusrsock: process host network syscall with critical section
if config_walltime_signal is enabled, NuttX_sim will receive a lot of
signals, the socket api will break and errno will be EINTR, masking irq
before calling the host socket api will avoid this problem.

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-06-13 22:10:16 +08:00
zhangyuan21
6f8cb7edd3 arch/arm64: Save FPU context when a context switch occurs in SMP mode
In SMP mode, the fpu owner may switch from core0 to core1,
so it is necessary to force saving the FPU context when a
context switch occurs.

This PR fixed the crash issue mentioned in #8799.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-06-13 13:23:28 +09:00
Dong Heng
b24f931aca xtensa/esp32s3: Support 32MB SPI flash 2023-06-12 21:05:33 +08:00
chao an
2369e3cbc8 arm/dataabort: fix compile warning
Error: arm/arm_dataabort.c:146:10: error: format '%x' expects argument of type 'unsigned int',
                                          but argument 3 has type 'uint32_t' {aka 'long unsigned int'} [-Werror=format=]
  146 |   _alert("Data abort. PC: %08x FAR: %08x FSR: %08x\n",
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  147 |          regs[REG_PC], far, fsr);

Signed-off-by: chao an <anchao@xiaomi.com>
2023-06-12 13:36:08 +08:00
Xiang Xiao
da5e978341 mm: Correct the callsite of mm_mallinfo
forget to update in https://github.com/apache/nuttx/pull/9488

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-11 19:37:04 +03:00
Xiang Xiao
d920bfba10 mm: include malloc.h in mm/mm.h
to remove the forward declaration of mallinfo and mallinfo_task

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-06-11 19:37:04 +03:00
Petro Karashchenko
509a808e84 arch/arm/stm32f7: fix typo
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-06-11 12:55:29 +08:00
Petro Karashchenko
1b801a5bbc style: remove extra spaces and align parameters
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-06-11 12:55:29 +08:00
Petro Karashchenko
2a38c38b03 style: fix style issues found during code review
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-06-11 12:54:52 +08:00
Ville Juven
37bf542c9e mpfs/mpfs_shead.S: Remove MMU mappings and flush TLB upon boot
This fixes warm reset crash when trying to access memory via old stale
MMU mappings
2023-06-10 01:36:59 +08:00
Ville Juven
7bc8e59cce riscv/kernel_stack: Use kernel stack to store the user context
If a kernel stack exists, use that whenever the user process is in
privileged mode, i.e. running an exception or in system call. Previously
the exception context was stored into the user's stack, which is not ideal.

Why?

1. Because the exception entry status (REG_INT_CTX) is needed by the
   kernel, and this is now in user memory which requires that the correct
   user mappings are active when it is accessed.

2. The user must currently account for the exception stack frame (which
   is BIG) in its own stack allocation. Moving the exception context save
   to the kernel stack offloads this responsibility from the user to the
   kernel, which is IMO the correct behavior.

3. The kernel access to user memory is currently allowed without condition,
   however this is not ideal either. The privileged mode status CSR allows
   blocking access to user memory via the STATUS_SUM-bit, which should be
   disabled by default and only enabled when access to user space is really
   needed. This patch allows implementing such features.
2023-06-09 13:53:27 +08:00
Ville Juven
a636edcbe4 addrenv/kstack: Allocate the kernel stack before initializing tcb
This is preparation to use kernel stack for everything when the user
process enters the kernel. Now the user stack is in use when the user
process runs a system call, which might not be the safest option.
2023-06-09 13:53:27 +08:00
anjiahao
7732791cd6 mempool:Add mail_info support for multiple pools
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-06-08 23:56:40 +08:00
Fotis Panagiotopoulos
b89215a11f Fixed Kconfig options for the obsolete GD32F4_TICKLESS_SYSTICK & STM32WB_TICKLESS_SYSTICK options. 2023-06-07 11:10:34 -06:00
SunJ
ad4e2f0922 arch/riscv: Fixed FPU context save/restore error
Always save/restore FPU context if the current thread use FPU

Signed-off-by: SunJ <jsun@bouffalolab.com>
2023-06-07 16:39:51 +03:00
Fotis Panagiotopoulos
a57cd563d5 stm32: Removed unused Kconfig option.
The option STM32_TICKLESS_SYSTICK is not used anywhere and the
stm32 arch does not have the capability to use systick as a
tickless timer.
2023-06-07 09:40:55 -03:00
chenwen@espressif.com
617927f27c xtensa/esp32: Support multiple PHY init data bin
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-06-07 16:44:26 +08:00
GD32-MCU
fdfc25cf56 add sdio driver for GD32F4 2023-06-07 16:43:55 +08:00