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19212 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
1967805b91 risc-v: Fix format specifier in debug log 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-04-28 01:18:46 +08:00
chao.an
042640abbf arch/arm: add support for GCC LTO 
1. Enable GCC link-time optimizer
2. Enable use of a linker plugin during link-time optimization

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:54 +08:00
chao.an
cbef8681fe arch/risc-v: add support for GCC LTO 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8 OpenSBI: Add riscv_hardfp.S to compilation 
It will just become an empty object if FPU support is not included.
 2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs. 2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
98d8d2a1ff arch/xtensa: Group all the macros in one file. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
Abdelatif Guettouche
541eabb535 xtensa_int_handlers.S: Refactor the calls to ps_setup. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 08:57:53 -03:00
chao.an
db54b0b836 arm/assert: fix build warning on clang 
common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat]
             stack, ptr[0], ptr[1], ptr[2], ptr[3],
             ^~~~~
include/debug.h:119:59: note: expanded from macro '_alert'
   __arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
                                      ~~~~~~              ^~~~~~~~~~~

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-27 14:18:42 +08:00
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-26 11:34:28 +03:00
Abdelatif Guettouche
aaa5316235 arch/xtensa: Simply use xtensa_createstack for CPU1 idle task. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-26 01:36:54 +08:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork 
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
 2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:23:03 +03:00
Xiang Xiao
e9f5eb0823 boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:22:46 +03:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Ville Juven
2580520828 RISC-V: Fix system crash when FPU is in use 
FPU registers need to be written prior to updating CSR_STATUS
 2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d boards: Move -fno-common from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 07:57:29 +03:00
Abdelatif Guettouche
3942f4d133 arch/xtensa: No need to save SP in EXCSAVE_1 when linking the interrupt 
frame with the previous frame.  The SP is already saved in A12.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
f130d8c143 xtensa_user_handler.S: Fix backtrace. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
7a3ad4b224 xtensa_user_handler.S: Use the ps_setup macro when dealing with an 
exception.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-23 10:19:23 +08:00
Xiang Xiao
5a565e753c pm: Move pm_initialize call from driver_initialize to xxx_pminitialize 
since it's too late with the below commit:
ommit a594a5d7a8
Author: chao.an <anchao@xiaomi.com>
Date:   Mon Apr 11 19:44:26 2022 +0800

    sched/init: drivers_initialize() should be late than up_initialize()

    up_initialize
    |
     ->up_serialinit
       |
        ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

    drivers_initialize
    |
     ->syslog_console_init
       |
        ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-22 14:36:27 +03:00
Masayuki Ishikawa
04f81ecddb arch: risc-v: Do not enable FPU for K210 with QEMU 
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
  if FPU is disabled.
- This commit fixes this issue.

Impact:
- K210 with QEMU only

Testing:
- Tested with qemu-5.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-04-22 14:52:04 +08:00
Huang Qi
06c7a3ca59 arch/risc-v/riscv_misaligned: Implement float load/store support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-22 12:23:10 +08:00
Huang Qi
be95e76910 arch/risc-v: Enable FPU for K210 
K210 support rv64gc ISA, now we enable F/D extension for it.

Note: QEMU for K210 don't support FPU now.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 21:47:29 +03:00
chao.an
1c8e12406e compile/opt: add config DEBUG_LINK_MAP 
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
chao.an
64d7326ed5 compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS 
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
Abdelatif Guettouche
56ecd44f63 arch/xtensa: Color the other CPUs task when they are created. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-22 01:12:55 +08:00
Xiang Xiao
1320e5add4 arch/arm: Move the duplicated assembly code to common folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-21 12:56:34 +03:00
Xiang Xiao
ebf1093cff arch/arm: Switch the context of save and restore from assembler to c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-21 12:56:34 +03:00
Huang Qi
0332b78f99 arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 15:26:05 +08:00
chao.an
875c5dac75 arm/armv[7|8]m: compare of hardware fp registers should skip REG_FP_RESERVED 
Fix fpu test break

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 14:55:54 +09:00
Abdelatif Guettouche
64e4c9ca02 arch/xtensa: Move xtensa_save_context to up_saveusercontext for 
consistency with other archs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-21 01:59:34 +08:00
Abdelatif Guettouche
6db910a1aa arch/xtensa: Use syscall interface for xtensa_save/restore_context. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-21 01:59:34 +08:00
chao.an
0315283c21 arch/clang: add support for Clang LTO 
add support of Clang's Link Time Optimization (LTO) on NuttX build system

Reference:
https://gcc.gnu.org/onlinedocs/gccint/LTO-Overview.html
https://llvm.org/docs/LinkTimeOptimization.html

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 01:21:54 +08:00
chao.an
67fbfda974 arch/armv6-m: add support of LLVM Clang 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-21 01:21:54 +08:00
Huang Qi
48b81bda09 arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-20 16:08:17 +03:00
Alin Jerpelea
dda675779a arch: arm: mor1kx: remove empty files 
during contribution empty files have been pushed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
af98967439 arch: arm: stm32l4: remove empty files 
during contribution empty files have been pushed.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
73cd86dad7 arch: arm: phy62xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
22ceda26bb arch: arm: lpc43xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
4e19a97916 arch: arm: imxrt: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Alin Jerpelea
208b892efe arch: arm: cxd56xx: Add Apache license to files 
In the initial contribution those files were missing the license

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-04-20 21:05:45 +08:00
Huang Qi
95ab7b973b arch/sparc,xtensa: Control output by $(Q) as other arch 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-20 12:04:17 +02:00
zhuyanlin
8d756a75a2 armv7/r:cp15_cache_all: fix error in LineSize 'r5' mask 
r5 = r3 & r1

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-04-20 08:06:58 +09:00
chao.an
fc3565e9eb arch/z80: Unify the toolchain definition of SDCC for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
0cf8088406 arch/misoc: Unify the toolchain definition of GNU for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
e066d5d1e0 arch/risc-v: Unify the toolchain definition of RVG for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
2df591b3bb arch/armv7-a/r: Unify the toolchain definition of eabi for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
4a085e1cdb arch/arm/armv6-m: Unify the toolchain definition of eabi for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
2246afcdd8 arch/armv7-m: Unify the toolchain definition of eabi/clang/iar for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
chao.an
a79bf8c9eb arch/armv8-m: Unify the toolchain definition of eabi/clang for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
Ville Juven
5b6dd876b8 risc-v/riscv_assert.c Fix dumping of status from ISR 
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
 2022-04-19 15:28:09 +03:00
Ville Juven
5c951d8c4a arm/arm_assert.c Fix dumping of status from ISR 
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
 2022-04-19 15:28:09 +03:00
chao.an
b110c984b1 arch/armv7-[a|r]: correct the handing of group env switch 
This PR resolved 2 issues:
1. CURRENT_REGS is not set correctly on swint handling
2. group env is not changed properly

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 12:10:25 +03:00
Xiang Xiao
96fa8be5f5 arch/armv[7|8]-m: Compare all FPU registers in up_fpucmp 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 11:09:36 +03:00
Xiang Xiao
d80c2d7419 arch/arm: Remove all lazy fpu related code 
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 14 18:07:14 2022 +0800

    arm/armv7-[a|r]: move fpu save/restore to assembly handler

    Save/Restore FPU registers in C environment is dangerous practive,
    which cannot guarantee the compiler won't generate the assembly code
    with float point registers, especially in interrupt handling

    Signed-off-by: chao.an <anchao@xiaomi.com>

commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date:   Thu Apr 7 13:48:04 2022 +0800

    arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only

    Signed-off-by: chao.an <anchao@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 11:09:36 +03:00
Xiang Xiao
7c5b2e3305 arch/arm: Remove FAR and CODE from common/ and arm*/ folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 00:23:59 +03:00
Xiang Xiao
7a0fd8d10f arch/risc-v: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 00:22:45 +03:00
Xiang Xiao
84b0453ef3 arch/arm: Remove unneeded group_addrenv call which handled by arm_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 22:18:32 +03:00
Xiang Xiao
2e7b10356f arch/sparc: Remove unneeded group_addrenv call which handled by up_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
d28892e454 arch/xtensa: Remove unneeded group_addrenv call which handled by xtensa_irq_dispatch 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
ef62e1c970 arch/misoc: Remove unneeded group_addrenv call which handled by [lm32|minerva]_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
Xiang Xiao
9fad9ed66b arch/mips: Remove unneeded group_addrenv call which handled by mips_doirq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-18 18:34:12 +03:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch 
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext() 
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
chao.an
bdbbdbe242 arm/a1x: fix compile break 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 10:02:17 +08:00
Xiang Xiao
ef1a98dd00 Remove the unneeded void cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
Xiang Xiao
32ee2ae407 Remove the unneeded worker_t cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
Xiang Xiao
373363d750 arch/arm: Move arm_signal_dispatch.c to common folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:30:41 +03:00
wangbowen6
91d02f5db8 arm/arch: using __builtin_frame_address(0) implement up_getsp(). 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-18 00:49:15 +08:00
Xiang Xiao
6af167c086 arch/sparc: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
977fa987e2 arch/mips: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
1ce592e8b5 arch/misoc: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
3c82094156 arch/or1k: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
0bd9a66305 arch/x86_64: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
af00e016e9 arch/sim: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
e923875c1b arch/ceva: Remove FAR from chip folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
Xiang Xiao
6bc61b5752 arch/xtensa: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 18:42:38 +03:00
chao.an
c08d9047b2 arch/Toolchain.defs: replace all ${/$} with $(/$) 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-17 00:58:34 +08:00
chao.an
aed21ba0bc arch/armv[7|8]m: enhance the clang support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-17 00:58:34 +08:00
okayserh
3a015d56b0 Fixed a compile error, presumably caused by C&P error. 2022-04-16 19:21:10 +08:00
Jan Charvat
6ec86361a8 arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
e28584131d arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller driver. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
0fa1541a80 arch/riscv/esp32c3: esp32c3_twai.h TWAI (CAN) controller registers provided by Espressif. 
File provided by Abdelatif Guettouche

Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Huang Qi
a94c865791 arch/risc-v: Use fs status definition from csr.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-15 19:41:31 +08:00
Petro Karashchenko
09b3fb25ab drivers: remove unimplemented open/close/ioctl interfaces 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-15 16:56:25 +08:00
Richard Tucker
1b13d1b440 arch/arm/src/sam34/Kconfig: fix typo in device name 2022-04-15 02:22:01 +08:00
Richard Tucker
de66e18d6f arch/arm/src/sam34/sam_hsmci.c: SAM3X GPIO setup 2022-04-15 02:22:01 +08:00
Richard Tucker
929556d750 arch/arm/src/sam34/sam_hsmci: DMA also present on SAM3X chips 2022-04-15 02:22:01 +08:00
Richard Tucker
be0bcac91b arch/arm/src/sam34/sam_hsmci.c: DMA setup before write is required 2022-04-15 02:22:01 +08:00
Richard Tucker
bc7f4b2375 arch/arm/src/sam34/sam_hsmci.c: delay required after sending command 2022-04-15 02:22:01 +08:00
chao.an
dc961baaea arm/armv7-[a|r]: move fpu save/restore to assembly handler 
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 22:33:10 +08:00
Alan C. Assis
c232be541c Add SPIRAM to ESP32-S2 2022-04-14 22:10:23 +08:00
Ville Juven
47945e83b2 MPFS: Set correct interrupt per mode (M-/S-mode) for mtimer 2022-04-14 16:36:06 +03:00
Xiang Xiao
a94b7b9cca arm/rtl8720c: Remove up_getsp which is already implemented in arch/arm/arch.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-14 16:35:52 +03:00
chao.an
b3d47e246f arch/stack_color: correct the stack top of running task 
This PR to ensure the stack pointer is locate to the stack top

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
chao.an
0c79ad9d8d arch/[arm|sparc]: replace INT32_ALIGN_* to STACK_ALIGN_* 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
Ville Juven
c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use 
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
 2022-04-14 16:43:34 +08:00
Ville Juven
3d6ab5c804 RISC-V: Add SBI glue logic 
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
 2022-04-14 16:43:34 +08:00
Abdelatif Guettouche
a5c64adbe4 arch/Kconfig: Move the DUMP_ON_EXIT option out of the Bring-up group. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
6d12ee19e2 arch: Move the DUMP_ON_EXIT logic after nxtask_exit. 
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group.  Accessing the group from dumponexit will crash.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
d6c952c56f arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT 
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
   filelist = tcb->group->tg_filelist;"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Ville Juven
190e3aded3 MPFS: Use riscv_exception_attach like the others do 
Exception / fault handling goes to unexpected ISR, fix by setting the
common ISR handlers like all other RISC-V platforms do.
 2022-04-13 21:56:21 +08:00
Ville Juven
2b29dec5e0 MPFS: Fix mtimecmp address 
MTIMECMP0 was incorrect
 2022-04-13 21:56:21 +08:00
Huang Qi
f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler 
FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Huang Qi
898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register 
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function 
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
 2022-04-13 12:00:40 +02:00
chao.an
0d7ea348d5 arm/armv8-m: indicating no low-overhead-loop predication by default 
Fix usage fault on clang version 13.0.0 (-Ofast):
------------------------------------------------------------------
| arm_hardfault: Hard Fault escalation:
| arm_usagefault: PANIC!!! Usage Fault:
| arm_usagefault:  IRQ: 3 regs: 0x3c58c510
| arm_usagefault:  BASEPRI: 00000080 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 00000004
| arm_usagefault:  CFSR: 00020000 HFSR: 40000000 DFSR: 00000000 BFAR: 01608050 AFSR: 00000000
| arm_usagefault: Usage Fault Reason:
| arm_usagefault:  Invalid state
| up_assert: Assertion failed at file:armv8-m/arm_usagefault.c line: 113 task: lpwork
| backtrace:
| [ 2] [<0x2c58124a>] up_backtrace+0xa/0x2e2
| [ 2] [<0x2c56f7cc>] sched_dumpstack+0x28/0x66
| [ 2] [<0x2c580cd0>] up_assert+0x62/0x254
| [ 2] [<0x2c56ab8a>] _assert+0/0xa
| [ 2] [<0x2c55575a>] nxsched_add_prioritized+0x38/0xa2
| [ 2] [<0x2c555894>] nxsched_add_blocked+0x2e/0x44
| [ 2] [<0x2c580748>] up_block_task+0x2a/0x96
| [ 2] [<0x2c5569ea>] nxsem_wait+0x64/0xb4
| [ 2] [<0x2c556a40>] nxsem_wait_uninterruptible+0x6/0x10
| [ 2] [<0x2c559b9a>] work_thread+0x1c/0x48
-------------------------------------------------------------------

usage fault on 0x2c55575a:

------------------------------------
|2c555722 <nxsched_add_prioritized>:
|; {
|2c555722: 80 b5         push  {r7, lr}
|...
|2c55575a: 2f f0 17 c0   le  0x2c555732 <nxsched_add_prioritized+0x10> @ imm = #-44
|...
------------------------------------

Arm v8-M Architecture Reference Manual:

C2.4.103 LE, LETP

B3.28 Low overhead loops:

An INVSTATE UsageFault is raised if a LE instruction is executed and FPSCR.LTPSIZE does not read as four.
When a new floating-point context is created and FPCCR.ASPEN is set to zero it is the responsibility of software
to correctly initialize FPSCR.LTPSIZE.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:39:22 +08:00
chao.an
ff210e1c2d arch/stack_color: correct the end address of stack color 
The different optimization of compilers will cause ambiguity in
obtaining sp through up_getsp() in arm_stack_color(), if compile
with clang and enable the optimization flag (-Ofast), up_getsp()
call will be earlier than push {r0-r9,lr}, the end address of color
stack will overlap with saved registers.

Compile line:
clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \
-mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o  arm_checkstack.o

Assembler code:
llvm-objdump -aS arm_checkstack.o
------------------------------------
|00000000 <arm_stack_color>:
|;   start = INT32_ALIGN_UP((uintptr_t)stackbase);
|       0: c2 1c         adds  r2, r0, #3
|       2: 22 f0 03 02   bic r2, r2, #3
|;   end   = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
|       6: 19 b1         cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6
|       8: 08 44         add r0, r1
|       a: 20 f0 03 00   bic r0, r0, #3
|       e: 00 e0         b 0x12 <arm_stack_color+0x12> @ imm = #0
|;   __asm__
|      10: 68 46         mov r0, sp                               <--- fetch the sp before push {r7 lr}
|      12: 80 b5         push  {r7, lr}                           <--- sp changed
|;   nwords = (end - start) >> 2;
|      14: 80 1a         subs  r0, r0, r2
|      16: 80 08         lsrs  r0, r0, #2
|; }
|      18: 08 bf         it  eq
|      1a: 80 bd         popeq {r7, pc}
|      1c: 4b f6 ef 63   movw  r3, #48879
|      20: cd f6 ad 63   movt  r3, #57005
|      24: a0 ee 10 3b   vdup.32 q0, r3
|;   while (nwords-- > 0)
|      28: 20 f0 01 e0   dlstp.32  lr, r0
|;       *ptr++ = STACK_COLOR;                                    <--- overwrite
|      2c: a2 ec 04 1f   vstrw.32  q0, [r2], #16
|      30: 1f f0 05 c0   letp  lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8
|; }
|      34: 80 bd         pop {r7, pc}
------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:37:54 +08:00
Xiang Xiao
df5a8a53ae arch/arm: Move FPU initialization to common place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 23:35:06 +03:00
Abdelatif Guettouche
7660b3b1c4 riscv/riscv_schedulesigaction.c: Remove the duplicate state saving. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-12 21:18:59 +03:00
Xiang Xiao
2094f4f0dc arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 21:01:14 +03:00
Huang Qi
72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 01:10:49 +08:00
Ville Juven
48fa6c1280 arch/risc-v: Add missing DMB to mtimer / setmtimecmp 
The memory mapped mtimecmp lives in I/O space so must add barrier
to make sure the value sticks. Otherwise a new IRQ might fire
at once.
 2022-04-12 21:33:19 +08:00
chao.an
5ec4df2cc6 risc-v/c906: fix build break 
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
   DEBUGASSERT(lower);
   ^~~~~~~~~~~
cc1: all warnings being treated as errors

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 15:49:52 +03:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-12 12:14:40 +03:00
Lingao Meng
a56199c7dd sim: bt: Add specific bluetooth HCI number id 
Add option for attached the local bluetooth device use
specific bluetooth HCI number id.

Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
 2022-04-12 15:15:25 +08:00
SPRESENSE
39f7c4aea0 arch: cxd56xx: Fix critical section in scu driver 
Add critical section to scu one-shot sequencer.
 2022-04-12 07:55:00 +09:00
SPRESENSE
e725829547 cxd56xx/cxd56_emmc.c: Fix compile warning 
Add necessary include header named debug.h for using ferr and
finfo.
 2022-04-12 07:55:00 +09:00
SPRESENSE
5be940080b arch: cxd56xx: update loader and gnssfw version 
Update loader and gnssfw to version 2.2.20585
 2022-04-12 07:55:00 +09:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu 
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
 2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Ville Juven
d5ea259828 RISC-V: Combine 3 variables that depend on CPU amount into one 
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.

The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
 2022-04-12 01:59:35 +08:00
Xiang Xiao
a90bdda1ae arch/riscv: Add mtimer driver 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-11 10:59:18 +03:00
Ville Juven
a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes. 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
779fc6461f riscv/esp32c3: Use the common exception handler. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
e8134a8b57 riscv/riscv_exception_common.S: Allow chips to define the exception 
section.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
875dd46207 riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core 
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
36bc8d2131 arch/risc-v: Align prototype of riscv_exception with xcpt_t 
Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Xiang Xiao
c235c0fa43 boards/lx_cpu: Enable up_perf API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Xiang Xiao
1f7b49d700 boards/nucleo-h743zi2: Enable up_perf API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Huang Qi
c6942b68d5 arch/risc-v: Add handler for misaligned load/store 
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.

In this patch, we handle the misaligned access by software to make
system run continue.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-08 23:27:07 +08:00
chao.an
8d66dbc068 arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-08 14:28:41 +09:00
Huang Qi
b6cf1ac662 arch/riscv: Minor style change and text correction 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-08 01:07:06 +08:00
Huang Qi
4ebc581c73 esp32c3: Simplify irq dispatch logic 
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-07 18:16:35 +02:00
Ville Juven
d38b4965f8 MPFS: Prepare support for S-mode 
- Access to PLIC via S-mode registers
- Access to IRQs via S-mode registers / definitions
- Initialize S-mode registers upon boot
- Initialize per CPU area before nx_start

NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
 2022-04-07 21:55:36 +08:00
Xiang Xiao
3a26cf6a02 arch/risc-v: Remove the unnecessary inclusion of board header files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-07 11:25:12 +03:00
Jiuzhu Dong
d87cf8d4ca fs/poll: change format for type pollevent_t 
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2022-04-07 12:14:06 +08:00
Huang Qi
53fef8d9c4 arch/risc-v: Replace riscv_fault with riscv_exception 
Remove riscv_fault since its code is duplicated with riscv_exception,
and there are textual excpetion reason in riscv_exception.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-06 22:48:46 +08:00
yinshengkai
db012687f9 arch/sim: support simulator keyboard devices 2022-04-06 15:26:57 +03:00
Alan C. Assis
1090e1a8ea xtensa/esp32: Add support to TWAI/CANBus controller 2022-04-06 15:09:46 +03:00
zhuyanlin
6a761ff087 arch:tcbinfo: update tcbinfo as xcpcontext update 
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-04-05 13:33:00 +02:00
Ville Juven
6c22e2894c RISC-V: Fix usage of static_assert in riscv_percpu.c 
There is no alias for struct riscv_percu_s
 2022-04-04 22:44:25 +08:00
Ville Juven
7db356e720 RISC-V: Fix file name of riscv_dispatch_syscall 2022-04-04 22:44:18 +08:00
Petro Karashchenko
d08fbca679 nuttx: unify FAR attribute usage across the code 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-04 21:32:58 +08:00
Abdelatif Guettouche
f527abc324 arch/xtensa: Build the xtensa_tcbinfo.c file for S2 and S3. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-04 21:25:47 +08:00
Xiang Xiao
bf48c6d4a8 arch/riscv: Rename SCRATCH_HARTID_OFFSET to RISCV_PERCPU_HARTID_OFFSET 
and fix the typo error

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-04 08:22:08 +03:00
Petro Karashchenko
9b7f9867aa arch/risc-v: use STACK_FRAME_SIZE for in S-mode syscall asm 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-04 12:05:53 +08:00