Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran
This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Especially the write calibration must bail out if the memory test timeouts,
otherwise the device will get stuck in running the memory test in sequence,
and it will always timeout.
Negative error value was also not properly returned from mpfs_mtc_test.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It doesn't make sense to try to auto-determine write latency, it may pass with too low value.
Keep the existing implementation if the write latency has been set to minimum
value, otherwise just set it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Commit 50a8ec6 broke many mmc devices. Only if the flag
priv->caps & SDIO_CAPS_4BIT_ONLY was set, it migth work.
Without the flag, the mmc clock is never set (mmcsd_widebus()
call is terminated early stopping the clock). This flag
is probably not very generic because most mmc hw support
1, 4 and 8 bit modes.
JEDEC specifies a bus width selection procedure, but it's
not implemented in this mmcsd_sdio.c driver. Thus, it's
not known whether the hw supports 1, 4 anf 8 bit modes or
a combination of them.
However, with priv->caps & SDIO_CAPS_4BIT_ONLY the driver
suddenly assigns priv->buswidth = MMCSD_SCR_BUSWIDTH_4BIT
making it the only way to have the driver working.
Fix this by relaxing the above mentioned restrictions.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Provide a way to only customize specific string operations,
such as for memcpy with the DMA capability by ROM.
Signed-off-by: yangdongdong <yangdongdong@xiaomi.com>
When I try to set priorities in certain programs, such as init_priority(HIGH_PRIORITY), I've noticed that during linking, there's no guarantee that the programs will be compiled in the sequence I've specified based on priority. This has led to some runtime errors in my program.
I realized that in the ld file, when initializing dynamic arrays, there's no assurance of initializing init_array.* before init_array. This has resulted in runtime errors in the program. Consequently, I've rearranged the init_array.* in the ld file of NuttX to be placed before init_array and added a SORT operation to init_array.* to ensure accurate initialization based on priorities during linking.
This commit adds basic support for electrically isolated 8 bit expander.
The expander communicates with the MCU via SPI interface. Both single
and multiple pin read are supported.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
isx019 driver freezes by I2C access in the interrupt context.
This I2C access is intended to stop data output from FPGA.
Delete this I2C access for the following reasons.
- Data output from FPGA does not affect power consumption
- There are no problems in capture restart without data output stop
since restart is done by image data block first.
If scheduling occurs in file_fsync,
fl_lock may be released, and an error may
occur when calling nxmutex_unlock
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
This commit adds support for galvanic isolated ISO1H812G SPI expander.
Both single pin and multiple pin writes are supported.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
when func `nuttx_export_kconfig` is called for the second time,
the expired configuration will be retained causing compilation failure
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
