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Author SHA1 Message Date
François Schauber
0bfacf4d12 include/threads.h: add missing semi-colon 2021-08-24 00:14:12 +08:00
Alan C. Assis
6031e06ff2 Move "Contributing" to be after getting started 2021-08-23 21:22:49 +08:00
Alin Jerpelea
07d528fd8d license: Ken Pettit: update licenses to Apache 
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-23 11:41:41 +08:00
chao.an
6cfb132232 arch/cortex-m: replace arm_switchcontext to c-style 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-22 14:44:01 +08:00
Abdelatif Guettouche
6c2fcdc45d Documentation: Update ESP32-C3 supported peripheral list. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-21 18:30:53 -03:00
chao.an
efaf72a1b1 net/local: correct the return length of sendmsg 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:59:59 +08:00
chao.an
68d6dbf86f arch/riscv/assert: enhance the assert dump 
enhance the assert dump to show the all tasks info including backtrace and registers

[    7.617000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init
[    7.617000] [ EMERG] riscv_dumpstate: Call Trace:
[    7.617000] [  INFO] [BackTrace| 3|0]:  0x4202001e 0x42007cb4 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd0 0x42009894
[    7.617000] [  INFO] [BackTrace| 3|1]:  0x4200a62e 0x42008e8a 0x4200841e 0x42008320 0x42005ad0 0x42001a56
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200bdd0
[    7.617000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074
...
...
[    7.617000] [ EMERG] riscv_showtasks: Tasks status:
[    7.617000] [ EMERG] riscv_taskdump: Idle Task: PID=0
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=596 of 976
[    7.617000] [  INFO] [BackTrace| 0|0]:  0x4200787e 0x3fc94ff0
[    7.617000] [ EMERG] riscv_registerdump: EPC:4200787e
[    7.617000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074
...
[    7.617000] [ EMERG] riscv_taskdump:
[    7.617000] [ EMERG] riscv_taskdump: hpwork: PID=1
[    7.617000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016
[    7.617000] [  INFO] [BackTrace| 1|0]:  0x420082a6 0x4200328c 0x42001ab4 0x42001a42
[    7.617000] [ EMERG] riscv_registerdump: EPC:420082a6
[    7.617000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000
...

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:58:21 +08:00
chao.an
333191becd riscv/backtrace: add up_backtrace support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-21 14:56:34 +08:00
Abdelatif Guettouche
2925d4956b xtensa/esp32: Use up_cpu_index instead of this_cpu. 
this_cpu requires sched.h to be included.
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5d626f7267 xtensa/esp32_irq.c: Hard code special IRQs in the IRQ map. These IRQs 
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
56a7f3b651 arch/xtensa/esp32: Update the drivers regarding the API change in IRQ 
handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5be9f24fe5 arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted. 
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
97dca8fe10 arch/xtensa/esp32: Use the same g_intenable shadows in cpuint.c and 
irq.c

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
633cdf8e27 arch/xtensa/esp32: Map NuttX's IRQs to ESP32 CPU interrupts. 
This map also keeps track of the CPU that attached the IRQ.  This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
chao.an
c826c37277 nuttx/up_backtrace: add up_backtrace interface 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-20 13:11:45 -03:00
chao.an
904348302a sched/backtrace: simplify the assign of tcb in case of negative pid 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-20 13:11:45 -03:00
Sara Souza
e092c457e6 xtensa/lx7: Fix the CROSSDEV variable 2021-08-20 16:48:20 +02:00
Jiuzhu Dong
ccaea473f3 endian.h: add prefix for __LITTLE/__BIG_ENDIAN, __BYTE_ODRER 
Change-Id: If072b69e37a89ccd6dc62e1d485b15703da029ac
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-08-20 07:47:07 -07:00
Jiuzhu Dong
1f93071370 byteswap.h: add byteswap.h header file 
Change-Id: I2b00618f608efbb8834328823b5e0eaa66f42aba
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-08-20 07:47:07 -07:00
Xiang Xiao
af72376773 fs: Remove magic field from partition_info_s 
since it is wrong and impossible to return file
system magic number from the block or mtd layer.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 09:19:52 -03:00
Antti Vähälummukka
3421a0be38 drivers/timers/Kconfig: Increase PWM_NCHANNELS range to 1..16 2021-08-20 08:56:30 -03:00
Antti Vähälummukka
6eb73ced51 arch/risc-v/src/mpfs: Add CorePWM driver 
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA

This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
 2021-08-20 08:56:30 -03:00
Alin Jerpelea
bed0f50182 Kconfig: add NuttX License setup for BSD components 
This commit will add a build option to enable BSD code in License setup.

NOTE: When this option is enabled components with BSD licenses can be
added to the build. Please make sure that the licenses match your
project.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-20 01:45:00 -07:00
Alin Jerpelea
c7a2da8acf update licenses to Apache 
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-08-20 01:45:00 -07:00
chao.an
c19edbd08e net/rpmsg: add nonblock connect(2) support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 22:25:44 -07:00
chao.an
498830d3f4 net/rpmsg: fix typo in comment 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 22:25:44 -07:00
chao.an
afef9c2044 net/rpmsg: move the sync handshark to ns_bind callback 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 22:25:44 -07:00
chao.an
64e95dc1f5 net/rpmsg: simplify the socket timeout of connect 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 22:25:44 -07:00
Jiuzhu Dong
dc97ee9b36 fs/mount: fix crash becauseof bad release order 
N/A

Change-Id: I850f0706f4554d140a86f935b8dce07d23beedaf
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-08-19 20:44:18 -07:00
Jiuzhu Dong
35b3898ce1 task_spawn: release g_spawn_parmsem and sched_unlock at the ending 
Change-Id: Ifcb5b9921e82fc495c4457fdb5f0607f40b07fc0
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-08-19 20:43:54 -07:00
chao.an
9701a678bd net/tcp: add nonblock connect(2) support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 19:19:05 -07:00
chao.an
1a55d933ef net/local: add nonblock connect(2) support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 19:18:52 -07:00
chao.an
ee3980abd7 driver/pipe: add nonblock open support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 19:18:52 -07:00
Abdelatif Guettouche
11ed9199c1 Documentation/esp32-wrover-kit: update the name of the GPIO interrupt 
device.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-19 19:18:23 -07:00
Masayuki Ishikawa
cb167c3f7d sched: Allow CONFIG_SMP_NCPUS=1 without CONFIG_DEBUG_FEATURES 
Summary:
- This commit allows CONFIG_SMP_NCPUS=1 without CONFIG_DEBUG_FEATURES

Impact:
- None

Testing:
- Tested with sim:smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-08-19 19:17:56 -07:00
Xiang Xiao
4b41579ccf arch/armv8-m: Add SAU support 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-20 10:22:43 +09:00
raiden00pl
06cf12617c nucleo-f446re: add 3-phase Hall effect sensor support 2021-08-19 08:19:38 -07:00
raiden00pl
dbe4cd88dd boards/stm32/common: add 3-phase Hall effect sensor common logic 2021-08-19 08:19:38 -07:00
raiden00pl
78962165d8 arch/stm32: add 3-phase Hall effect sensor lower half 2021-08-19 08:19:38 -07:00
raiden00pl
b30f5e146d drivers/sensors: add an upper half 3-phase Hall effect sensor driver 2021-08-19 08:19:38 -07:00
Abdelatif Guettouche
15fb70cb00 libs/libxx: Download C++ libraries during context. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-19 03:05:54 -07:00
SPRESENSE
9732334b5d net/socket: Fix bug that sendto did not return an error 
When `tolen` is not 0 and `to` is NULL, it causes illegal buffer access.
Add a parameter check in this condition.
 2021-08-19 01:31:05 -07:00
SPRESENSE
d17d877764 net/local: Fix receive data size calculation for local_recvmsg 
In psock_dgram_recvfrom function, fix code logic.
 2021-08-19 01:31:05 -07:00
chao.an
1060953567 sched/backtrace: add sched_backtrace support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 01:30:50 -07:00
chao.an
83964231a5 libs/libc: move the backtrace implement to sched 
1. move the backtrace implement to sched
2. rename CONFIG_UNWINDER to CONFIG_SCHED_BACKTRACE

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 01:30:50 -07:00
chao.an
0a8d951837 arch/arm: correct the frame pointer register declare 
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-08-19 01:26:07 -07:00
SPRESENSE
38bfadbeb9 drivers/sensors/bmp280.c: Correct bmp280 driver 
There were some mistakes in porting to the common sensors, and they
caused the following problems.

- Hardfault by bmp280_set_interval
- Read data always zero
 2021-08-18 23:22:21 -07:00
SPRESENSE
f8d036d70b drivers/Makefile: Use the -include directive for platform/Make.defs 
Since `platform` of `platform/Make.defs` is a symbolic link created during
the build process, we use -include directive instead of include for safety.
 2021-08-18 23:21:47 -07:00
Abdelatif Guettouche
0ac02765bd libs/libxx/uClibc++.defs: Download the correct file type. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 12:19:16 -07:00
Abdelatif Guettouche
cd0f64d779 xtensa/irq.h: Add a macro to convert to an IRQ from a peripheral ID. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-18 10:49:58 -03:00