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26 Commits

Author SHA1 Message Date
Gregory Nutt
6455f60c60 Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures 2014-08-08 18:39:28 -06:00
Gregory Nutt
a1b862580b Fix an error introduced in the last commit 2014-04-19 07:54:52 -06:00
Gregory Nutt
6f26d834b6 LPC17xx, TIVA, and Kinetis interrupt initialization: use the NVIC ICTR register to determine how many interrupt lines/registers are supported by the MCU 2014-04-17 14:51:53 -06:00
Gregory Nutt
1061e67f14 Fix error in last ARMv7-M up_disable_irq checkin 2014-01-15 15:26:32 -06:00
Gregory Nutt
e43f86071d Fix all Cortex-M3/4 implementations of up_disable_irq(). They were doing nothing. Thanks to Manuel Stühn for the tip. 2014-01-15 09:56:30 -06:00
Gregory Nutt
4de5e40669 Individual IRQs are not longer disabled on each interrupt. See ChangeLog for detailed explanation 2014-01-15 08:09:19 -06:00
Gregory Nutt
3855ce04e8 Beginning of high priority nested interrupt support for the ARMv7-M family 2013-12-21 11:03:38 -06:00
Gregory Nutt
8b317e9ea3 Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts 2013-08-03 08:22:37 -06:00
Gregory Nutt
3aa94411be Remove up_assert_code 2013-04-25 15:19:59 -06:00
patacongo
65fb38bbcf Add support for ram vectors to the ARMv7-M architecture 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5756 42af7a65-404d-4744-a932-0658087f49c3
 2013-03-18 21:10:08 +00:00
patacongo
a001227981 Use of BASEPRI to control ARM interrupts is now functional 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5548 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 16:09:10 +00:00
patacongo
30d1159097 More logic to use BASEPRI to control interrupts -- still doesn't work 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5547 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 14:37:17 +00:00
patacongo
5ab31d456e Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-22 01:25:40 +00:00
patacongo
a62640f1be Refactor all lpc17xx header files (more like STM32 header file structure now) 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5534 42af7a65-404d-4744-a932-0658087f49c3
 2013-01-18 19:16:44 +00:00
patacongo
5347c159fb Add LPC43 interrrupt control logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4905 42af7a65-404d-4744-a932-0658087f49c3
 2012-07-04 19:34:11 +00:00
patacongo
1e4fe73e6b Add PIC32 SPI driver 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4459 42af7a65-404d-4744-a932-0658087f49c3
 2012-03-07 00:53:50 +00:00
patacongo
8eee445400 Fix some LPC17xx GPIO/button interrupt logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4246 42af7a65-404d-4744-a932-0658087f49c3
 2011-12-31 23:09:33 +00:00
patacongo
f93b962f28 Name change: Change Cortex-M3 naming to ARMv7-M naming so support Cortex-M4 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3846 42af7a65-404d-4744-a932-0658087f49c3
 2011-08-05 21:57:49 +00:00
patacongo
7bb3b4c8a1 current_regs should be volatile; add support for nested interrupts; enable interrupts during syscall processing 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3475 42af7a65-404d-4744-a932-0658087f49c3
 2011-04-06 23:01:06 +00:00
patacongo
a864ab2137 Attach mem mgmt fault handle if MPU is enabled 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3471 42af7a65-404d-4744-a932-0658087f49c3
 2011-04-06 01:51:07 +00:00
patacongo
826d5a706f Add lpc17xx GPIO interrupts + fixes needed by last apps-build check-in 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3413 42af7a65-404d-4744-a932-0658087f49c3
 2011-03-24 02:26:25 +00:00
patacongo
b283cb1e4f Add beginning of m9s12x GPIO support 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3317 42af7a65-404d-4744-a932-0658087f49c3
 2011-02-25 23:05:37 +00:00
patacongo
8c0e236c6f Add logic to clear pending EMAC interrupts 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3118 42af7a65-404d-4744-a932-0658087f49c3
 2010-11-18 01:36:04 +00:00
patacongo
26687ad87f misc updates 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3116 42af7a65-404d-4744-a932-0658087f49c3
 2010-11-17 03:16:26 +00:00
patacongo
1ca1e7029b Correct IRQ handling, calibrate delay loops 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2759 42af7a65-404d-4744-a932-0658087f49c3
 2010-06-23 01:56:31 +00:00
patacongo
0f2e501caa Add interrupt control logic 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2733 42af7a65-404d-4744-a932-0658087f49c3
 2010-06-06 17:11:15 +00:00