The MPFS eMMC DMA has some requirements that are only fulfilled by
enabling separate DMA access buffers (FAT DMA buffers) and by forcing
indirect access to the media via FAT_FORCE_INDIRECT.
Why? Direct access to user buffers violates two things:
- Buffer alignment is not ensured
- Buffers are user memory (problematic in BUILD_KERNEL)
- There are occasional extra STOPs being sent due to an IP bug when using an
FPGA based I2C. Add a flag "inflight" to mask out extra STOP interrupts when
using the FPGA based implementation
- There are no MPFS_I2C_ST_STOP_SENT irq's "initally". It is just already
either success or still in progress
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This adds initialization of the ksz9477 switch when used instead of
a PHY, directly connected to SGMII
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Add a function to read PolarFire's serial number from system controller, and use the first five digits as device's mac address
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Workaround to avoid deadlock situation: The RX shall not try to wait for complete
frame in case there is RX errors detected.
In case mpfs_receive is called, it keeps waiting for complete frame and
also keeps the net_lock locked. In the mean while, the TX may run out of free
descriptors, but can not get net_lock mutex lock to be able to release used
descriptors. If there are no free TX descs it disables RX interrupts because
it may require to send response to the received frame.
So, TX side keeps RX interrupts disabled due to lack of free descriptors and
RX blocks TX to release those descs by stubbornly waiting for complete frame.
RPMSG is associated with the use of HPWORK / LPWORK queues.
After sending a message to the remote end (Linux), the system
waits for an ack before proceeding. Unfortunately this may
take sometimes more time than one would expect. Ack waiting is
also unnecessary: nothing is done with that information. Even
worse, the net_lock() is also held during the blocked time so
it blocks other network stacks that are unrelated to this.
Also reorganize the mpfs_opensbi_*.S so that the trap
handler is easily relocated in the linker .ld file without
the need to relocate the utils.S. This makes it easier to
separate the files into own segments. The trap file should be
located in the zero device.
Moreover, provide support for simultaneous ACK and message
present handling capabilities in both directions. There are
times when both bits are set but only other is being handled.
In the end, the maximum throughput of the RPMSG bus increases
easily 10-20% or even more.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
SiFive document: "ECC Error Handling Guide" states:
"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."
Clean the cache at this early stage so no ECC errors will be flooding later.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Check that the base address and region size are properly aligned with
relation to each other.
With NAPOT encoding the area base and size are not arbitrary, as when
the size increases the amount of bits available for encoding the base
address decreases.
Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran
This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Especially the write calibration must bail out if the memory test timeouts,
otherwise the device will get stuck in running the memory test in sequence,
and it will always timeout.
Negative error value was also not properly returned from mpfs_mtc_test.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It doesn't make sense to try to auto-determine write latency, it may pass with too low value.
Keep the existing implementation if the write latency has been set to minimum
value, otherwise just set it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Calculate how long an I2C transation will take in microseconds, and use
this as the timeout for mpfs_i2c_sem_waitdone.
The reason for doing this is not to keep an i2c bus reserved for the full
1 second timeout, if e.g. a sensor is not on the bus / is faulty and
non-responsive. Reading the other sensors will be blocked for a relatively
long time (1 second) in this case. This fixes such behavior.
1 page might not be enough, if the task has a bigger stack. Best effort
is to allocate the default amount, however this won't work will all
tasks either.
Currently TX_FIFO_SIZE is not altered in mpfs_ep_set_fifo_size(),
but all paths (RX and TX) change MPFS_USB_RX_FIFO_SIZE only.
Fix the TX_FIFO_SIZE setup.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds a config flag to remove manual bclksclk training if one wants
to just use the controller's own training.
Manual addcmd training depends on the manual bclksclk training, so this
also adds this dependency in Kconfig.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Adds a platform specific implementation for tickless schedular operation. This includes:
- Tickless operation for vexriscv cores.
- Tickless operation for vexriscv-smp cores.
- Ticked operation for vexriscv-smp cores.
Ticked operation for vexriscv core has been refactored.
Additional default configuration added to demonstrate operation.
Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting，solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.
This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion
To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization
Signed-off-by: wangming9 <wangming9@xiaomi.com>
