* Documentation/guides/cortexmhardfaults.rst:
New. Migrated from [1] with conversion to reStructuredText,
minor typo fixes, and a link to a Narkive archive of the
original quoted question.
* Documentation/guides/index.rst:
Add above to TOC.
[1] https://cwiki.apache.org/confluence/display/NUTTX/Analyzing+Cortex-M+Hardfaults
Whenever a SPI flash operation is going to take place, it's
necessary to disable both the instruction and data cache. In order
to avoid the other CPU (if SMP is enabled) to retrieve data from
the SPI flash, it needs to be paused until the current SPI flash
operation finishes. All the code that "pauses" the other CPU (in
fact, the CPU spins until `up_cpu_resume` is called) needs to run
from the instruction RAM.
This config also prevents crashes due to the commit 6be363f, which
fix a race condition in multi-threaded write/read of the serial
driver, but increases stack size.
SAMv7 QSPI peripheral does not copy-in/out directly into/from
user provided buffer, but use a dedicated memory that is interfaces
using byte copy. The QSPI command buffer can point to memory with
any alignment
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Add a new field to record the global on the basis of mm_backtrace.
When using alloc, the field is incremented by 1,
so that the memory usage can be dumped within the range
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
armv8r and armv8a have different process affinity,
and sgi affinity needs to be able to adapt all of them.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary
For ARM64, it need to set IRQ type(EDGE or LEVEL). it's specific
for ARM64 PPI or SPI.
The change add arm64_gic_irq_trigger to set IRQ type
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
add up_affinity_irq/up_trigger_irq/up_prioritize_irq for gicv3
these interface is necessary for some drivers
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which
is following gic v3 and v4.
Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Patch 17:
virtio: follow virtio 1.2 spec, add more virtio status and device
Patch 18:
virtio: decoupling the transport layer and virtio device layer
1. Add virtio device api to decouple the transport layer and virtio
device layer.
2. Move the vrings info and virtqueue allocation/free to the
remoteproc transport layer;
3. Because 2, modify the rpmsg device also;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
The compiler will optimize boot_early_memset to memset,
but memset in libc cannot be used before MMU is enabled.
Therefore, assembly language is used to implement the
initialization of bss to avoid this problem.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
* Documentation/guides/nestedinterrupts.rst:
New. Imported from [1] and converted from CWIKI to reStructuredText.
* Documentation/guides/index.rst:
Link to the new page.
* Documentation/guides/zerolatencyinterrupts.rst:
Replace link to the CWIKI Nested Interrupts page with link to the
above.
[1] https://cwiki.apache.org/confluence/display/NUTTX/Nested+Interrupts
