In addition to the problems that were previously identified there were a few other bits and pieces outstanding;
* Timing was dependent on CPU speed rather than absolute time
* End of transfer handling was a bit mixed up
* It's possible for data to still be in the FIFO (i.e. not have reached
the card) when a next write is requested, so we need to wait for that to
complete
* Interrupt Status could be carried over from one transfer episode to the
next, corrupting progress
* Multi-descriptor DMA writing simply wasn't implemented, but there were no
indications ... it just failed silently
Master imxrt
* imxrt:Fix typos bit# and names
* imxrt:wdog Registers are 16 Bits
* imxrt:wdog Update has to be within 255 clocks of unlock
* imxrt:clockconfig Fix comments
* imxrt1050-evk:board.h Fix comments
* imxrt:imxrt_ccm.h Define Mux Selects for board.h use
* imxrt:clockconfig Allow better control from board.h
1) Allows a board config clock setting to be defined
in terms of the /n values shown in Figure 18-2.
Clock Tree of the i.MX RT1050 Processor Reference
Manual, Rev. 1, 03/2018
2) Allows the clock multipelx selection to be made in
The board config.
* imxrt1050-evk:Define board clocking based on divisor and muxes
Approved-by: GregoryN <gnutt@nuttx.org>
* Clocks were wrongly configured - way too fast because there is no primary divider on LPC4330
This is fixed by means of changing the definitions in the board.h file. I've edited the one for the lpc4330-xplorer board because I'm actually working with Versiboard and don't want to contribute that config just yet while I've still got the drains up on it.
* The LPC43_SDMMC_DELAY register was not being set
I suspect, in the 'real world', it's possible to get away without setting this, but I've added a register definition, default value and register access macros into arch/arm/src/lpc43xx/chip/lpc43_scu.h and then used them in arch/arm/src/lpc43xx/lpc43_sdmmc.c.
* The LPC43_SDMMC_BLKSIZ and LPC43_SDMMC_BYTECNT registers had the wrong values.
The management have already implemented a rather nice block level interface for the stm32 so I've just re-used that to write to these registers as required. I'm slightly nervous that accessing the configuration registers (SCR being the prime example) which has a much smaller block size may not be being done in the right way but it does seem to work correctly, so let's assume it's all OK until someone tells me otherwise.
These fixes have been tested with DMA-based read/write on a LPC4330. Speed via nsh is pretty low but I'm assuming that's just a buffering/implementation issue for now.
Improvements in STM32 PWM low level driver
stm32_pwm: remove some impossible PWM configurations
stm32_pwm: support for complementary outputs
stm32_pwm: deadtime configuration
stm32_pwm: output polarity and IDLE state configuration
nucleo-f302r8: pwm support
stm32f429i-disco: pwm support
configs: update some configurations according to changes in STM32 PWM driver
Approved-by: GregoryN <gnutt@nuttx.org>
(1) Now the Ethernet is completely re-initialized when an error occurs by means of taking the interface down and back up but the PHY is _not_ renegotiated for that case because that is very time consuming and an error in the Ethernet is no reflection on the state of the PHY anyway.
(2) Explicitly sets the expected PHY address to zero (this could be moved into the config) rather than searching for it which takes ages, and it's zero anyway for this board (that's the broadcast address, and anything that cannot respond on that has multiple PHYs, so that would be a new board).
(3) Allows for the renegotiation of the PHY to be optional when a reset is needed. If a non-renegotiated reset doesn't result in good comms to the PHY then it'll automatically be escalated to a renegotiated one.
(4) Only performs a reset for errors that need it (the CRITICAL_ERROR define). The list of errors that need reset are somewhat arbitrarily chosen based on my prejudices and might need to be revisited, but certainly the jabber errors don't need reset, the partial packet is thrown away by the layer above anyway.
(5) Re-loads the multicast table on reset.
(6) Adds a bit more logging into the imxrt Ethernet module.
arch/arm/src/lc823450: Fix up_allocate_heap() in lc823450_allocateheap2.c
For lc823450, heap area in flat build mode must start just after
_eronly. Because bss/data area is allocated in lower address than
text area in SRAM. See ld.scripts for details. Also, this change
removes unsed up_allocateheap.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: GregoryN <gnutt@nuttx.org>
Pull request for mtd/progmem refactoring.
* mtd/progmem: change up_progmem_npages to up_progmem_neraseblocks
page is a unit for read/write operation.
eraseblock is a unit for erase operation.
up_progmem_npages is a little bit confusing because it returns number of
erase blocks in flash memory. This patch changes up_progmem_npages to
up_progmem_neraseblocks. There is no logical change.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* mtd/progmem: up_progmem_erasesize.
Change argument name to be more readable.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* mtd/progmem: up_progmem_eraseblock
Change up_progmem_erasepage to up_progmem_eraseblock.
eraseblock is more readable name than erasepage.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* mtd/progmem: change up_progmem_eraseblock's return value.
up_progmem_eraseblock erase a block. so it's better to return the erase block
size than page size.
Signed-off-by: EunBong Song <eunb.song@samsung.com>
* arm/cortex-r : fix wrong cp15_flash_dcache.
change mcrne to mcr for unconditional dcache.
Signed-off-by: sungduk.cho <sungduk.cho@samsung.com>
Approved-by: GregoryN <gnutt@nuttx.org>
