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5693f26a5e
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10145 Commits

Author SHA1 Message Date
Gregory Nutt
5693f26a5e XMC4xx: Fix several early compilation problems. 2017-03-16 11:30:02 -06:00
Gregory Nutt
fe610e7a1d XMC4500 Relax: Add basic board support infrastructure of Infineon XMC4500 Relax Lite v1 2017-03-16 10:52:01 -06:00
Gregory Nutt
66d001d0e1 XMC4xxx: Initial clock configuration logic. 2017-03-16 09:48:57 -06:00
Gregory Nutt
059e398185 XMC4xxx: A few more SCU register bit definitions. 2017-03-15 18:50:48 -06:00
Gregory Nutt
450d747265 Merge remote-tracking branch 'origin/master' into xmc4 2017-03-15 13:10:17 -06:00
Gregory Nutt
519f14fbb5 XMC4xxx: A few more SCU register bit definitions. 2017-03-15 11:43:58 -06:00
Gregory Nutt
77f244ed7b XMC4xx: Add logic to get the CPU frequency. 2017-03-15 10:22:24 -06:00
Gregory Nutt
772b3cf21b XMC4xxx: Add Peripheral Memory Map header file. 2017-03-14 19:07:19 -06:00
Gregory Nutt
a635e7df7a XMC4xxx: Add SCU header file. 2017-03-14 16:19:30 -06:00
Gregory Nutt
2430049e3b arch/arm/include/xmc4: More support for Infineon XMC4xxx arch. Still incomplete. 2017-03-14 13:04:09 -06:00
Gregory Nutt
dc4ac48aad arch/arm/src/xmc4: Initial, partial support for Infineon XMC4xxx 2017-03-14 11:56:29 -06:00
Gregory Nutt
240d1e9b3b Update some comments 2017-03-14 11:39:10 -06:00
Gregory Nutt
c97581e99b Update some comments 2017-03-14 11:16:35 -06:00
Gregory Nutt
4a93b0dc0c Update comments. 2017-03-14 08:44:56 -06:00
David Cabecinhas
86400a252d ARM: Fix off-by-one interrupt stack allocation in 8-byte aligned architectures 2017-03-14 20:01:45 +08:00
Gregory Nutt
4d33f26717 Update some comments 2017-03-12 12:33:44 -06:00
Gregory Nutt
d9cdb6c383 STM32; OTG host implementations of stm32_in_transfer() must obey the polling interval for the case of isochronous and itnerrupt endpoints. 2017-03-12 08:39:30 -06:00
Gregory Nutt
98a98a0c8b Minor change for consistency with a previous commit. 2017-03-12 07:20:10 -06:00
Gregory Nutt
9b11187b2a STM32 OTG HS: A little research reveals that only the F2 RCC initialization set the OTGHSULPIEN bit and Photon is the only F2 board configuration that uses OTG . Therefore, we can simplify the conditional logic of the last PR. Negative logic was used (#ifndef BOARD_DISABLE_USBOTG_HSULPI) to prevent bad settings in other configurations. But give these facts, the preferred positive logic now makes more sense (#ifdef BOARD_ENABLE_USBOTG_HSULPI). 2017-03-11 18:00:38 -06:00
Gregory Nutt
e0f7b9582a STM32: Review of last STM32 F2 PR. Progate changes to STM32 F4 and F7 OTGHS. Rename some configs/photon/src files. Naming can be either photon_ or stm32_ but must be consistent. 2017-03-11 16:31:11 -06:00
Simon Piriou
11876dc090 Merged in spiriou/nuttx/usb_fix (pull request #265) 
stm32f20xxx: add BOARD_DISABLE_USBOTG_HSULPI flag

Approved-by: Gregory Nutt
 2017-03-11 22:04:51 +00:00
Simon Piriou
70d8f0189d stm32f20xxx: add BOARD_DISABLE_USBOTG_HSULPI flag 2017-03-11 18:15:18 +01:00
David Sidrane
cdfc158f90 up_initialize.c edited online with Bitbucket 2017-03-11 15:40:48 +00:00
David Sidrane
c9ecb3c378 As discovered by dcabecinhas. This fix assume the 8 byte alignment options for size stack size or this will overwrite the first word after TOS 
See https://github.com/PX4/Firmware/issues/6613#issuecomment-285869778
 2017-03-11 15:35:03 +00:00
Gregory Nutt
aadf6c6e16 STM32 F33: Fix another error in ADC base address usage. 2017-03-10 17:49:32 -06:00
Gregory Nutt
852b189910 STM32 F33 ADC: Correct bad definitions of base addresses; Fix naming collision by changing colliding STM32_ADC12_BASE to STM32_ADC12_CMN_BASE 2017-03-10 17:46:19 -06:00
Gregory Nutt
24816cb08b All STM32 host drivers. In IN endpoint retry, delay for a clock tick to give some breathing space for the CPU. EXPERIMENTAL change. 2017-03-10 10:25:43 -06:00
David Sidrane
2baffab16e WS 2017-03-10 15:42:59 +00:00
David Sidrane
acaebb361b STM32, STM32 F7, and STM32 L4: Clone Freddie Chopin's I2C change to similar STM32 I2C drivers. 
Save elapsed time before handling I2C in stm32_i2c_sem_waitstop()
   This patch follows the same logic as in previous fix to
   stm32_i2c_sem_waitdone().
   It is possible that a context switch occurs after I2C registers are read
   but before elapsed time is saved in stm32_i2c_sem_waitstop(). It is then
   possible that the registers were read only once with "elapsed time"
   equal 0. When scheduler resumes this thread it is quite possible that
   now "elapsed time" will be well above timeout threshold. In that case
   the function returns and reports a timeout, even though the registers
   were not read "recently".
   Fix this by inverting the order of operations in the loop - save elapsed
   time before reading registers. This way a context switch anywhere in the
   loop will not cause an erroneous "timeout" error.
 2017-03-10 05:07:39 -10:00
Freddie Chopin
3cd66af889 ave elapsed time before handling I2C in stm32_i2c_sem_waitstop() 
This patch follows the same logic as in previous fix to
stm32_i2c_sem_waitdone().

It is possible that a context switch occurs after I2C registers are read
but before elapsed time is saved in stm32_i2c_sem_waitstop(). It is then
possible that the registers were read only once with "elapsed time"
equal 0. When scheduler resumes this thread it is quite possible that
now "elapsed time" will be well above timeout threshold. In that case
the function returns and reports a timeout, even though the registers
were not read "recently".

Fix this by inverting the order of operations in the loop - save elapsed
time before reading registers. This way a context switch anywhere in the
loop will not cause an erroneous "timeout" error.
 2017-03-10 07:35:10 -06:00
Gregory Nutt
9cd3f7f80a STM32, STM32 F7, STM32 L4: OTG host drivers: Do not do data toggle if interrupt transfer is NAKed. Sugested by webbbn@gmail.com 2017-03-09 15:07:31 -06:00
Simon Piriou
6768831851 Merged in spiriou/nuttx (pull request #257) 
STM32F2: add USB OTG HS support for stm32f20xxx cores

Approved-by: Gregory Nutt
 2017-03-09 20:06:12 +00:00
Gregory Nutt
04297d1b0f Update some comments 2017-03-09 13:57:37 -06:00
Gregory Nutt
a3b4475474 STM32, STM32 F7, and STM32 L4: Back out part of 3331e9c49a. Returning immediately int he case of a NAK makes the Mass Storage Class driver unreliable. The retry/timeout logic is necessary. This implementation tries to implement a compromise: If a NAK is received after some data is received, then the partial data received is returned as with 3331e9c49a. If if a NAK is received with no data, then no longer returns the NAK error immediately but retries until data is received or a timeout occurs. Initial testing indicates that this fixes the issues the MSC. However, I hae concerns that if multiple sectors are read in one transfer, there could be NAKs between sectors as well and, in that case, then change will still cause failures. 2017-03-09 13:49:25 -06:00
Simon Piriou
31aef4a9c0 STM32F2: add USB OTG HS support for stm32f20xxx cores 2017-03-09 20:30:32 +01:00
David Sidrane
c8efeecfda Merged in david_s5/nuttx/upstream_kinetis (pull request #256) 
Kinetis:Allow Board to add Pullups on SDHC lines

Approved-by: Gregory Nutt
 2017-03-09 15:34:12 +00:00
David Sidrane
2700fd9e81 Kinetis:Allow Board to add Pullups on SDHC lines 2017-03-09 05:30:02 -10:00
Gregory Nutt
ee5ae3a57d STM32, STM32 F7, and STM32 L4: Clone Freddie Chopin's I2C change to similar STM32 I2C drivers. 2017-03-09 07:37:52 -06:00
Freddie Chopin
5a6d95dd9f ave elapsed time before handling I2C in stm32_i2c_sem_waitdone() 
It is possible that a context switch occurs after stm32_i2c_isr() call
but before elapsed time is saved in stm32_i2c_sem_waitdone(). It is then
possible that the handling code was executed only once with "elapsed
time" equal 0. When scheduler resumes this thread it is quite possible
that now "elapsed time" will be well above timeout threshold. In that
case the function returns and reports a timeout, even though the
handling code was not executed "recently".

Fix this by inverting the order of operations in the loop - save elapsed
time before handling I2C. This way a context switch anywhere in the loop
will not cause an erroneous "timeout" error.
 2017-03-09 07:29:12 -06:00
Gregory Nutt
92858d1096 Cosmetic changes from review of a previous PR 2017-03-09 07:00:44 -06:00
Andreas Bihlmaier
d5cb3f5a32 Merged in andreasBihlmaier/nuttx/fixes-lpc43_ssp (pull request #253) 
actually write modified value to register

Approved-by: Gregory Nutt
 2017-03-09 12:54:47 +00:00
Andreas Bihlmaier
ce908cec9c Merged in andreasBihlmaier/nuttx/fixes-lpc43_i2c (pull request #252) 
use correct macro for irqid (fortunately both point to LPC43_IRQ_EXTINT+18)

Approved-by: Gregory Nutt
 2017-03-09 12:53:56 +00:00
Andreas Bihlmaier
55bd808dcc Merged in andreasBihlmaier/nuttx/fixes-lpc43_ethernet (pull request #251) 
fix logic in preprocessor checks and correct arguments to lpc43_pin_config initialization

Approved-by: Gregory Nutt
 2017-03-09 12:53:22 +00:00
Andreas Bihlmaier
1c5ededc48 Merged in andreasBihlmaier/nuttx/fixes-lpc43_adc (pull request #250) 
fix logic error in lpc43_adc

Approved-by: Gregory Nutt
 2017-03-09 12:52:33 +00:00
Andreas Bihlmaier
871756b6c0 Merged in andreasBihlmaier/nuttx/fixes-lpc43_sct_and_sgpio_headers (pull request #249) 
Fix errors in LPC43 SCT and SGPIO headers.

Approved-by: Gregory Nutt
 2017-03-09 12:52:03 +00:00
Andreas Bihlmaier
be90fbd1a1 Merged in andreasBihlmaier/nuttx/fixes-lpc43_gpdma (pull request #248) 
rename LPC43_GPDMA_GLOBAL_CONFIG (already slipped previous commit C file); fix GPDMA_CONTROL_SBSIZE_*, improve usability of GPDMA_CONTROL_{S,D} macros

Approved-by: Gregory Nutt
 2017-03-09 12:51:20 +00:00
Andreas Bihlmaier
9227947543 Merged in andreasBihlmaier/nuttx/fixes-lpc4310203050_pinconfig (pull request #247) 
add missing PINCONF_INBUFFER in several places of lpc4310203050_pinconfig.h

Approved-by: Gregory Nutt
 2017-03-09 12:50:45 +00:00
Andreas Bihlmaier
9ba4ce0bb9 Merged in andreasBihlmaier/nuttx/change-adc0_mask (pull request #246) 
change Kconfig type of ADC0_MASK from hex to int; add ADC driver options to lpc43xx

Approved-by: Gregory Nutt
 2017-03-09 12:49:58 +00:00
ahb
7835e5bde8 actually write modified value to register 2017-03-09 11:33:09 +01:00
ahb
0dee37ffb3 use correct macro for irqid (fortunately both point to LPC43_IRQ_EXTINT+18) 2017-03-09 11:29:01 +01:00