Summary:
- Remove unnecessary d-cache operation to make boot fast
Impact:
- armv7-a SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds L2CC to smp/defconfig
- Also adds CLOCK_MONOTONIC
Impact:
- sabre-6quad:smp only
Testing:
- Tested with both QEMU and dev board
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit adds L2CC to nsh/defconfig
- Also adds EXAMPLES_HELLO, TESTING_GETPRIME and TESTING_OSTEST
Impact:
- sabre-6quad:nsh only
Testing:
- Tested with both QEMU and dev board
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
MAX11612: 4 channels VCC=5V0 Int VRef=4.096V
MAX11613: 4 channels VCC=3V3 Int VRef=2.048V
MAX11614: 8 channels VCC=5V0 Int VRef=4.096V
MAX11615: 8 channels VCC=3V3 Int VRef=2.048V
MAX11616: 12 channels VCC=5V0 Int VRef=4.096V
MAX11617: 12 channels VCC=3V3 Int VRef=2.048V
Note: The chips' auto-scanning feature is not supported in this revision.
Summary:
- This commit fixes armv7-a deadlocks with D-cache in SMP mode.
- In SMP mode, MMU for SDRAM area must be set to shareable
Impact:
- SMP only
Testing:
- Tested with sabre-6quad:smp (QEMU and dev board)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed waitpid_test stops with lc823450-xgevk:rndis
- The condition was CONFIG_DEBUG_ASSERTION=y
- Actually, the child task sent SIGCHILD but the parent couldn't catch the signal
- Then, I found that nx_waitid(), nx_waitpid() use sched_lock()
- However, a parent task and a child task are running on different CPUs
- So, sched_lock() is not enough and need to use a critical section
- Also, signal handling in nxtask_exithook() must be done in a critical section
Impact:
- SMP only
Testing:
- Tested with ostest with the following configurations
- lc823450-xgevk:rndis (CONFIG_DEBUG_ASSERTION=y and n)
- spresense:smp
- spresense:wifi_smp (NCPUS=2 and 4)
- sabre-6quad:smp (QEMU)
- esp32-core:smp (QEMU)
- maix-bit:smp (QEMU)
- sim:smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
arch/arm/src/stm32/hardware/stm32_dmamux.h,
arch/arm/src/stm32/hardware/stm32g47xxx_dmamux.h:
* New files, based on STM32G474RE reference manual, RM0440 Rev 4.
Used reference manual for STM32G071CB. The F0 and L0 families do not
appear to have a DMAMUX.
arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h:
* Remove all mentions of DMAMUX12 from comments. This family has
at most DMAMUX1 only.
* Add missing defines DMAMUX_CCR_SPOL_NONE,
DMAMUX_CCR_SPOL_RISING, DMAMUX_CCR_SPOL_FALLING, and
DMAMUX_CCR_SPOL_BOTH.
* DMAMUX_CCR_SYNCID_SHIFT: Fix comment. Was "Bits 24-26" (3 bits)
but datasheet shows bits 24-28 (5 bits).
* DMAMUX_CCR_SYNCID_MASK: Fix mask. Was 0x7 (3 bits) but datasheet
shows (5 bits) 0x1f.
* DMAMUX1_CSR_SOF(x): Add parenthesis around macro parameter
expansion.
* DMAMUX1_CFR_SOF(x): Rename to DMAMUX1_CFR_CSOF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX_RGCR_GPOL_MASK: Fix incorrect mask. Was 0x7 (3 bits) but
datasheet shows only 2 bits (0x3).
* Add missing defines DMAMUX_RGCR_GPOL_NONE,
DMAMUX_RGCR_GPOL_RISING, DMAMUX_RGCR_GPOL_FALLING, and
DMAMUX_RGCR_GPOL_BOTH.
* DMAMUX_RGCR_GNBREQ_SHIFT: Fix incorrect value. Was 17 (collision
with DMAMUX_RGCR_GPOL_SHIFT) but datasheet and comment both show
this bitfield at bits 19-23.
* DMAMUX_RGCR_GNBREQL_MASK: Fix incorrect mask. Was 0x7 (3 bits)
but datasheet shows 5 bits (0x1f).
* DMAMUX1_RGSR_SOF(x): Rename to DMAMUX1_RGSR_OF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMUX1_RGCFR_SOF(x): Rename to DMAMUX1_RGCFR_COF(x) for
consistency with datasheet and add parenthesis around macro
parameter expansion.
* DMAMAP_MAP(d,c): Add parenthesis around macro parameter
expansion.
* Fix nxstyle errors.
