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587145a881
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858 Commits

Author SHA1 Message Date
Abdelatif Guettouche
587145a881 riscv/Makefile: Delete old target used for debugging. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe Correct the code alignment found in review 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-26 11:34:28 +03:00
Ville Juven
6546789b7e RISC-V: Add syscall support for vfork 
If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
 2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c boards: Move -g from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 16:23:03 +03:00
Ville Juven
a014daf44f RISC-V: Add implementation for vfork 2022-04-25 15:44:32 +08:00
Ville Juven
2580520828 RISC-V: Fix system crash when FPU is in use 
FPU registers need to be written prior to updating CSR_STATUS
 2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d boards: Move -fno-common from Make.defs to Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-25 07:57:29 +03:00
Xiang Xiao
5a565e753c pm: Move pm_initialize call from driver_initialize to xxx_pminitialize 
since it's too late with the below commit:
ommit a594a5d7a8
Author: chao.an <anchao@xiaomi.com>
Date:   Mon Apr 11 19:44:26 2022 +0800

    sched/init: drivers_initialize() should be late than up_initialize()

    up_initialize
    |
     ->up_serialinit
       |
        ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

    drivers_initialize
    |
     ->syslog_console_init
       |
        ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-22 14:36:27 +03:00
Masayuki Ishikawa
04f81ecddb arch: risc-v: Do not enable FPU for K210 with QEMU 
Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
  if FPU is disabled.
- This commit fixes this issue.

Impact:
- K210 with QEMU only

Testing:
- Tested with qemu-5.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-04-22 14:52:04 +08:00
Huang Qi
06c7a3ca59 arch/risc-v/riscv_misaligned: Implement float load/store support 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-22 12:23:10 +08:00
Huang Qi
be95e76910 arch/risc-v: Enable FPU for K210 
K210 support rv64gc ISA, now we enable F/D extension for it.

Note: QEMU for K210 don't support FPU now.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 21:47:29 +03:00
chao.an
1c8e12406e compile/opt: add config DEBUG_LINK_MAP 
Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
chao.an
64d7326ed5 compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS 
Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-22 01:37:23 +08:00
Huang Qi
0332b78f99 arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-21 15:26:05 +08:00
Huang Qi
48b81bda09 arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-20 16:08:17 +03:00
chao.an
e066d5d1e0 arch/risc-v: Unify the toolchain definition of RVG for linux and windows 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-19 23:17:27 +08:00
Ville Juven
5b6dd876b8 risc-v/riscv_assert.c Fix dumping of status from ISR 
The status dump did not work if the first fault triggers before
the first context switch (during nx_start()).
 2022-04-19 15:28:09 +03:00
Xiang Xiao
7a0fd8d10f arch/risc-v: Remove FAR from chip and board folder 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-19 00:22:45 +03:00
chao.an
29005bd79f board/arch_fpu*: move arch_[get|cmp]fpu to common arch 
rename the arch api:
arch_getfpu  -> up_saveusercontext
arch_cmpfpu  -> up_cmpfpu

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
chao.an
5bdfae66ce arch/arm: export arm_saveusercontext() 
rename arm_saveusercontext() -> up_arm_saveusercontext()

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-18 22:22:16 +08:00
Xiang Xiao
ef1a98dd00 Remove the unneeded void cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
Xiang Xiao
32ee2ae407 Remove the unneeded worker_t cast 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-17 23:32:05 +03:00
chao.an
c08d9047b2 arch/Toolchain.defs: replace all ${/$} with $(/$) 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-17 00:58:34 +08:00
Jan Charvat
6ec86361a8 arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller included into Kconfig. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
e28584131d arch/riscv/esp32c3: ESP32C3 TWAI (CAN) controller driver. 
Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Jan Charvat
0fa1541a80 arch/riscv/esp32c3: esp32c3_twai.h TWAI (CAN) controller registers provided by Espressif. 
File provided by Abdelatif Guettouche

Signed-off-by: Jan Charvat <jancharvat.charvat@gmail.com>
 2022-04-15 22:55:26 +08:00
Huang Qi
a94c865791 arch/risc-v: Use fs status definition from csr.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-15 19:41:31 +08:00
Ville Juven
47945e83b2 MPFS: Set correct interrupt per mode (M-/S-mode) for mtimer 2022-04-14 16:36:06 +03:00
chao.an
b3d47e246f arch/stack_color: correct the stack top of running task 
This PR to ensure the stack pointer is locate to the stack top

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-14 16:48:19 +08:00
Ville Juven
c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use 
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
 2022-04-14 16:43:34 +08:00
Ville Juven
3d6ab5c804 RISC-V: Add SBI glue logic 
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
 2022-04-14 16:43:34 +08:00
Abdelatif Guettouche
6d12ee19e2 arch: Move the DUMP_ON_EXIT logic after nxtask_exit. 
Otherwise we will try to dump the state of the current task, however the
exit handler has already started doing some cleanup and invalidated its
group.  Accessing the group from dumponexit will crash.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Abdelatif Guettouche
d6c952c56f arch: Fix compile error when enabling CONFIG_DUMP_ON_EXIT 
"error: incompatible types when assigning to type 'struct filelist *' from type 'struct filelist'
   filelist = tcb->group->tg_filelist;"

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-13 21:59:23 +08:00
Ville Juven
190e3aded3 MPFS: Use riscv_exception_attach like the others do 
Exception / fault handling goes to unexpected ISR, fix by setting the
common ISR handlers like all other RISC-V platforms do.
 2022-04-13 21:56:21 +08:00
Ville Juven
2b29dec5e0 MPFS: Fix mtimecmp address 
MTIMECMP0 was incorrect
 2022-04-13 21:56:21 +08:00
Huang Qi
f5cf35784e arch/risc-v: Correct format of 32-bit insn in misaligned handler 
FIx:
Format specifies type 'unsigned long' but the argument has type 'uint32_t' (aka 'unsigned int')

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Huang Qi
898d789a5f arch/risc-v/riscv_misaligned: Correct sw source register 
If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 18:33:36 +08:00
Ville Juven
370152f3ba RISC-V: Move mhartid to own assembly macro+function 
Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.
 2022-04-13 12:00:40 +02:00
chao.an
ff210e1c2d arch/stack_color: correct the end address of stack color 
The different optimization of compilers will cause ambiguity in
obtaining sp through up_getsp() in arm_stack_color(), if compile
with clang and enable the optimization flag (-Ofast), up_getsp()
call will be earlier than push {r0-r9,lr}, the end address of color
stack will overlap with saved registers.

Compile line:
clang --target=arm-none-eabi -c "-Ofast" -fno-builtin -march=armv8.1-m.main+mve.fp+fp.dp \
-mtune=cortex-m55 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -D__NuttX__ -common/arm_checkstack.c -o  arm_checkstack.o

Assembler code:
llvm-objdump -aS arm_checkstack.o
------------------------------------
|00000000 <arm_stack_color>:
|;   start = INT32_ALIGN_UP((uintptr_t)stackbase);
|       0: c2 1c         adds  r2, r0, #3
|       2: 22 f0 03 02   bic r2, r2, #3
|;   end   = nbytes ? INT32_ALIGN_DOWN((uintptr_t)stackbase + nbytes) :
|       6: 19 b1         cbz r1, 0x10 <arm_stack_color+0x10> @ imm = #6
|       8: 08 44         add r0, r1
|       a: 20 f0 03 00   bic r0, r0, #3
|       e: 00 e0         b 0x12 <arm_stack_color+0x12> @ imm = #0
|;   __asm__
|      10: 68 46         mov r0, sp                               <--- fetch the sp before push {r7 lr}
|      12: 80 b5         push  {r7, lr}                           <--- sp changed
|;   nwords = (end - start) >> 2;
|      14: 80 1a         subs  r0, r0, r2
|      16: 80 08         lsrs  r0, r0, #2
|; }
|      18: 08 bf         it  eq
|      1a: 80 bd         popeq {r7, pc}
|      1c: 4b f6 ef 63   movw  r3, #48879
|      20: cd f6 ad 63   movt  r3, #57005
|      24: a0 ee 10 3b   vdup.32 q0, r3
|;   while (nwords-- > 0)
|      28: 20 f0 01 e0   dlstp.32  lr, r0
|;       *ptr++ = STACK_COLOR;                                    <--- overwrite
|      2c: a2 ec 04 1f   vstrw.32  q0, [r2], #16
|      30: 1f f0 05 c0   letp  lr, 0x2c <arm_stack_color+0x2c> @ imm = #-8
|; }
|      34: 80 bd         pop {r7, pc}
------------------------------------

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-13 09:37:54 +08:00
Abdelatif Guettouche
7660b3b1c4 riscv/riscv_schedulesigaction.c: Remove the duplicate state saving. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-12 21:18:59 +03:00
Xiang Xiao
2094f4f0dc arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-12 21:01:14 +03:00
Huang Qi
72e79aa0f1 arch/risc-v: Apply misaligned access handler for k210/bl602 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-13 01:10:49 +08:00
Ville Juven
48fa6c1280 arch/risc-v: Add missing DMB to mtimer / setmtimecmp 
The memory mapped mtimecmp lives in I/O space so must add barrier
to make sure the value sticks. Otherwise a new IRQ might fire
at once.
 2022-04-12 21:33:19 +08:00
chao.an
5ec4df2cc6 risc-v/c906: fix build break 
chip/c906_timerisr.c: In function 'up_timer_initialize':
Error: chip/c906_timerisr.c:71:3: error: implicit declaration of function 'DEBUGASSERT' [-Werror=implicit-function-declaration]
   DEBUGASSERT(lower);
   ^~~~~~~~~~~
cc1: all warnings being treated as errors

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 15:49:52 +03:00
Huang Qi
1975878835 arch/risc-v: Apply common mtime driver to mtime based chps 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-12 12:14:40 +03:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu 
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
 2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Ville Juven
d5ea259828 RISC-V: Combine 3 variables that depend on CPU amount into one 
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.

The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
 2022-04-12 01:59:35 +08:00
Xiang Xiao
a90bdda1ae arch/riscv: Add mtimer driver 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-11 10:59:18 +03:00
Ville Juven
a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes. 2022-04-10 08:27:10 +08:00