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Author SHA1 Message Date
zhuyanlin
30a2338e92 arch:esp: create chip.h header for chip src code. 
Create chip.h header for esp src code.
 2021-08-12 16:18:35 +02:00
zhuyanlin
6d592256fb arch:xtensa: add __ASSEMBLY__ for espxxx_soc.h 
Those header contain syntax not be recognize by gnu assembler.
 2021-08-12 16:18:35 +02:00
Alexander Vasiljev
4229099944 arch/arm/stm32h7: dma and serial: add TRBUFF flag. It is obligatory for uart. 2021-08-12 08:07:18 -03:00
Xiang Xiao
6b6c11f0ad mtd: Replace MTDIOC_XIPBASE with BIOC_XIPBASE 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-12 08:01:29 -03:00
Xiang Xiao
177e1ced3f Revert "mtd: Add MTDIOC_FLUSH IOCTL like MTDIOC_XIPBASE" 
to simplify flt and partion layer implementation

This reverts commit 2e49e1bc5c.
 2021-08-12 08:01:29 -03:00
Xiang Xiao
f4addbd640 mtd: Replace MTDIOC_PARTINFO with BIOC_PARTINFO 
to simplify flt and partion layer implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-12 08:01:29 -03:00
Alan C. Assis
1023918d37 Doc/esp32: Fix wapi psk command, value 1 is for WEP 2021-08-11 20:04:48 -07:00
Michal Lenc
c456b15916 Documentation: add guide for pysimCoder integration with NuttX 
This commit adds documentation for compiling NuttX for pysimCoder and
then running pysimCoder designed applications on NuttX. PysimCoder is
a Rapid Control Application Development Tool that can transfer block
diagrams into C code and can be used in real time control applications.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-11 18:04:09 +02:00
Xiang Xiao
d1687418db mtd: Remove the empty MTDIOC_XIPBASE implmentation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-11 09:50:51 -03:00
raiden00pl
610ac21240 nucleo-f302r8: add qenco example configuration 2021-08-11 09:30:12 -03:00
raiden00pl
736bcf035e nucleo-g431rb: add qenco example configuration 2021-08-11 09:30:12 -03:00
raiden00pl
f0b377f434 nucleo-f446re: add qenco example configuration 2021-08-11 09:30:12 -03:00
raiden00pl
8cb58213e5 nucleo-f103rb: add qenco example configuration 2021-08-11 09:30:12 -03:00
Xiang Xiao
76904371a1 fs: Remove endsector from partition_info_s 
since it can be computed from startsector and numsectors simply

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-11 09:26:43 -03:00
Gustavo Henrique Nihei
62fa4b0018 mtd: Translate BIOC_PARTINFO into MTDIOC_PARTINFO on FTL driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-10 19:45:14 -07:00
Gustavo Henrique Nihei
b321ae023c fs: Add ioctl command for retrieving partition info of a block device 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-10 19:45:14 -07:00
Gustavo Henrique Nihei
cddd9c9c38 mtd: Enable retrieval of MTD partition information 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-10 19:45:14 -07:00
Gustavo Henrique Nihei
6f5d02fb91 fs: Add data structure for Partition Information 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-08-10 19:45:14 -07:00
zhuyanlin
e333733053 xtensa:coproc: fix XTENSA_CP_ALLSET error in some case 
Consider follow coprocessor configuration case:

\#define XCHAL_CP_NUM                    1       /* number of coprocessors */
\#define XCHAL_CP_MAX                    2       /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK                   0x02    /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK              0x00    /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME                  "AudioEngineLX"
\#define XCHAL_CP1_IDENT                 AudioEngineLX
\#define XCHAL_CP1_SA_SIZE               208     /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN              8       /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX       1       /* coprocessor ID (0..7) */

In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.

Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
 2021-08-10 19:44:55 -07:00
Abdelatif Guettouche
054e284785 *_cpustart.c: Fix typos in function description. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-11 11:06:27 +09:00
Xiang Xiao
a09f262f1e fs/userfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-10 14:57:48 -03:00
Xiang Xiao
9d96c54b1b fs/unionfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-10 14:57:34 -03:00
Alan C. Assis
9d79f82e24 mmap: Fix note: initialize the variable 'ret' 2021-08-10 09:08:25 -07:00
Alan C. Assis
f3d1b6342c mkrd: Fix error: variable 'ret' is uninitialized 2021-08-10 09:08:25 -07:00
Alan C. Assis
e809c80f07 mtd/smartfs: Fix implicit conversion from 'int' to 'short' 2021-08-10 09:08:25 -07:00
Alan C. Assis
3309b8eee6 boards/sim: Add smartfs profile example 2021-08-10 09:08:25 -07:00
Fotis Panagiotopoulos
5b7ff03f40 lpc17_40: Fixed I2C port sanity check. 2021-08-10 09:04:33 -07:00
raiden00pl
2b3106fb47 Qencoder implementations for imxrt, stm32f7, stm32h7, stm32l4 and tivia don't support QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
51b24c4bad stm32/qenco: add support for QEIOC_SETPOSMAX 2021-08-10 11:19:05 -03:00
raiden00pl
dca8c65331 drivers/qencoder: add command to set the maximum encoder position 2021-08-10 11:19:05 -03:00
raiden00pl
092a0c8453 stm32/qenco: add an option to disable encoder timer extension from 16-bit to 32-bit 
Previous implementation has always expanded the width of the timer to 32-bit.
This feature is not always needed and should be configurable from Kconfig.
 2021-08-10 11:18:40 -03:00
raiden00pl
b0c9a6133e stm32/qenco: fix TIM2 width for STM32F3 which is 32-bit not 16-bit 
STM32F3 has timers of the same length as in STM32F4.
 2021-08-10 11:18:40 -03:00
raiden00pl
3dd385ac0c stm32/qenco: add support for STM32G4 
This required generalization of RCC definitions that are not compatible with previous chips
 2021-08-10 11:18:40 -03:00
raiden00pl
21f59c874f stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1 2021-08-10 11:18:40 -03:00
Sara Souza
af6c311fd1 risc-v/esp32-c3: Complete the support for RWDT 2021-08-10 11:17:15 -03:00
Sara Souza
61ab4f9f14 xtensa/esp32: Fix the type of enum passed between functions in esp32_rtc_clk 2021-08-10 11:15:51 -03:00
Sara Souza
67d29e7537 xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is. 2021-08-10 11:15:51 -03:00
Xiang Xiao
d7cb4567e6 fs/nfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-10 21:28:52 +09:00
Xiang Xiao
580de38832 fs/nfs: Return nanosecond from nfs_fstat and nfs_stat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-10 21:28:52 +09:00
Xiang Xiao
7a60efab35 fs/nfs: Support 64bit file length 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-10 21:28:52 +09:00
Alan C. Assis
c4742c2197 mtd/smartfs: Fix compilation warning 2021-08-09 20:33:05 -03:00
zhuyanlin
5820972727 arch:xtensa: add arch stdarg.h include file for xtensa 
Add arch/include/stdarg.h for xtensa.

Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
 2021-08-09 17:58:25 -03:00
Xiang Xiao
776458143c fs/hostfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
Xiang Xiao
6c61d032db fs: Add utimens and lutimens 
https://pubs.opengroup.org/onlinepubs/9699919799/functions/futimens.html
https://www.daemon-systems.org/man/utimens.2.html

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
Kenneth Thompson
50c49da078 bch/bchlib_cache.c: Fix error handling 2021-08-09 10:52:08 -07:00
Kenneth Thompson
9d29d4bef5 drivers/bch: Handle return value of bchlib_readsector() 2021-08-09 10:52:08 -07:00
Fotis Panagiotopoulos
59b9a30592 Compile fixes in MCP23X17 driver. 2021-08-09 08:42:53 -03:00
Xiang Xiao
7f60376d3a fs/hostfs: Change all priv_ to priv 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 13:20:19 +02:00
Alan C. Assis
2581c7acef Doc/FAQ: Add more entries about board initialization 2021-08-08 20:50:49 -07:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition 
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-07 09:20:10 -03:00