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9553 Commits

Author SHA1 Message Date
Gregory Nutt
7823a1680e Update a comment 2016-08-09 17:08:03 -06:00
Gregory Nutt
698d6d1294 SAM3/4: Extend clocking logic to enable clocking on ports D-F 2016-08-09 17:05:11 -06:00
Gregory Nutt
0918dd98ab Merged in gnagflow/nuttx (pull request #109) 
SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is configured as input.
 2016-08-09 16:40:48 -06:00
Gregory Nutt
fdcf0f7e5f Correct some comments 2016-08-09 15:15:21 -06:00
Wolfgang Reissnegger
cf35bb0b18 SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is configured as input. 
The value of a GPIO input is only sampled when the peripheral clock for
the port controller the GPIO resides in is enabled. Therefore we need
to enable the clock even when polling a GPIO.
 2016-08-09 13:23:05 -07:00
Gregory Nutt
b5b7a21bb6 Make reference count a uin16_t and save a couple of bytes. 2016-08-09 13:54:57 -06:00
Gregory Nutt
8b5833f7fe A consequence of Max's change to the logic to enable access to the backup domain is that every call to enabledbkp(true) must be followed by a matching call to enablebkp(false). There was one cse in both RTCC drivers where that may not always be true. 2016-08-09 11:33:47 -06:00
v01d
f715e9b787 RTC working, I2C in progress 2016-08-09 14:01:27 -03:00
Gregory Nutt
5d91b8cabb With last change, stm32_pwr_enablebkp() no longer returns a value 2016-08-09 07:50:31 -06:00
Max Neklyudov
1e3ccbac12 Make stm32_pwr_enablebkp thread safe 2016-08-09 07:36:13 -06:00
Alan Carvalho de Assis
8499f42bf9 Add STM32F37XX DMA channel configuration 2016-08-08 13:29:53 -06:00
Alan Carvalho de Assis
fcf1ae7e05 stm32f37xx: Fix SYSCFG_EXTICR_PORTE defined twice 2016-08-08 12:59:29 -06:00
Alan Carvalho de Assis
834f058573 I'm using NuttX on STM32F373 and saw the config was missing SPI2 and 
SPI3, see datasheet:
www.st.com/resource/en/datasheet/stm32f373cc.pdf

I searched for other members of STM32F37XX family and they also have 3 SPIs:
http://www.st.com/content/st_com/en/search.html#q=STM32F37-t=keywords-page=1
 2016-08-08 12:25:15 -06:00
Gregory Nutt
caea59b340 SPI bit order: Add configuration setting to indicate if an architecture-specif SPI implementation does or does not support LSB bit order. 2016-08-08 12:21:20 -06:00
Gregory Nutt
6df28bc74e Make bit-order SPI H/W feature configurable for better error detection 2016-08-08 11:54:13 -06:00
Gregory Nutt
c3cfd37791 Fix cloned variable error in all SPI drivers 2016-08-08 11:04:01 -06:00
Gregory Nutt
2ae3953f9e STM32/EFM32: If any hardware feature other and LSBFIRST is selected, return -ENOSYS. 2016-08-08 10:37:28 -06:00
Gregory Nutt
7d4cb73bd6 STM32 and EFM32 SPI drivers adopted an incompatible conventions somewhere along the line. The set the number of bits to negative when calling SPI_SETBITS which had the magical side-effect of setting LSB first order of bit transmission. This is not only a hokey way to pass control information but is supported by no other SPI drivers. 
This change three things:  (1) It adds HWFEAT_LSBFIRST as a new H/W feature.  (2) It changes the implementations of SPI_SETBITS in the STM32 and EFM32 derivers so that negated bit numbers are simply errors and it adds the SPI_HWFEATURES method that can set the LSB bit order, and (3) It changes all calls with negative number of bits from all drivers: The number of bits is now always positive and SPI_HWFEATUREs is called with HWFEAT_LSBFIRST to set the bit order.
 2016-08-08 08:28:13 -06:00
v01d
d483f7939f I2C0 support for kinetis/teensy-3.x (to be tested) 2016-08-06 22:23:59 -03:00
Gregory Nutt
56f2454c86 Fix names of pre-processor variables used in header file idempotence 2016-08-06 18:48:45 -06:00
Gregory Nutt
f5ae207516 Changes from Review of last PR adding Tiva PWM driver 2016-08-05 07:17:42 -06:00
Young
2994decd3c Add tiva PWM lower-half driver implementation 2016-08-05 18:53:25 +08:00
Gregory Nutt
d9314c1034 LPC43xx ADC: board.h should be included last; Also, unreleated, update tools/README.txt 2016-07-30 07:05:10 -06:00
Gregory Nutt
309480d0f9 Merge branch 'timekeeping' of bitbucket.org:nuttx/nuttx 2016-07-28 09:34:00 -06:00
Gregory Nutt
59f626313d Changes from review of last PR 2016-07-25 15:16:51 -06:00
Gregory Nutt
250b9d5597 Merged in JordanMacIntyre/nuttx/PWM_driver (pull request #106) 
Pwm_driver
 2016-07-25 14:59:45 -06:00
jmacintyre
f5ea811c97 create PWM driver, still having issues with building 2016-07-25 14:17:07 -05:00
Stefan Kolb
899a8aa2f0 SAMV7 TRNG: Missing endif. 2016-07-25 12:30:39 -06:00
Gregory Nutt
e895e19b9f Minor changes from review of last PR 2016-07-24 07:45:46 -06:00
Wolfgang Reissnegger
c0fa319f2b SAM3/4 UDP: Fix handling of endpoint RX FIFO banks. 
This fixes a race condition where the HW fills a FIFO bank while the SW is
busy, resulting in out of sequence USB packets.
 2016-07-23 20:11:04 -07:00
Wolfgang Reissnegger
cc191a977d SAM3/4 UDP: Remove redundant EP state assignment. 2016-07-23 20:11:03 -07:00
Wolfgang Reissnegger
f3a6a40f62 SAM3/4 Serial: Fix warning when CONFIG_SUPPRESS_UART_CONFIG is set. 2016-07-23 16:23:49 -07:00
Gregory Nutt
9b9b721406 Rename alarm_enable to rtc_alarm_enabled; mark inline 2016-07-23 12:01:57 -06:00
Gregory Nutt
5a0f9fcb7d Fix STM32 RTC Alarm interrupts. They were being enabled BEFORE the interrupt system was being initialized. 2016-07-23 10:36:06 -06:00
Gregory Nutt
14de4b99f8 Simplify some computations 2016-07-23 08:13:25 -06:00
Gregory Nutt
0984fcda44 Back out last RTC alarm changes. I am mistaken, the interrupts are enabled by stm32[l4]_exti_alarm(). 2016-07-23 07:53:08 -06:00
Gregory Nutt
65ac11692d STM32L4 RTC is cloned from F4; needs same fix. 2016-07-23 07:33:44 -06:00
Gregory Nutt
829c5610da STM32 F4 RTC ALARM: Was not enabling interrupts. 2016-07-23 07:19:14 -06:00
Gregory Nutt
e6137ff129 Rename SAMD/L version of CONFIG_GPIO_IRQ to CONFIG_SAMDL_GPIOIRQ 2016-07-22 14:38:33 -06:00
Gregory Nutt
3aea9b8bf3 Rename KL version of CONFIG_GPIO_IRQ to CONFIG_KL_GPIOIRQ 2016-07-22 14:34:21 -06:00
Gregory Nutt
5386403476 Rename Kinetis version of CONFIG_GPIO_IRQ to CONFIG_KINETIS_GPIOIRQ 2016-07-22 14:30:37 -06:00
Gregory Nutt
264578135d Rename LP11xx version of CONFIG_GPIO_IRQ to CONFIG_LPC11_GPIOIRQ 2016-07-22 14:23:31 -06:00
Gregory Nutt
360efe03c1 Rename LP17xx version of CONFIG_GPIO_IRQ to CONFIG_LPC17_GPIOIRQ 2016-07-22 14:18:30 -06:00
Gregory Nutt
369c942605 uint8_t is big enough for global. Range of values only 2-10 2016-07-21 15:18:27 -06:00
Gregory Nutt
67900beaaa LP43 Heap: REALLY eliminate the warning this time 2016-07-21 15:15:56 -06:00
Gregory Nutt
d5acc120a4 Kinetis K60: Fix some bad conditional compilation 2016-07-21 14:22:00 -06:00
Gregory Nutt
a2035f7efd Move include/nuttx/1wire.h to include/nuttx/drivers/1wire.h 2016-07-21 13:51:28 -06:00
Gregory Nutt
96d5b734a8 Add missing TWI definitions 2016-07-21 08:01:59 -06:00
Gregory Nutt
0d98507af1 Eliminate a warning 2016-07-20 16:47:23 -06:00
Gregory Nutt
1b9b3a7b47 pwm.h moved from include/nuttx/ to include/nuttx/drivers. 2016-07-20 13:48:24 -06:00
Gregory Nutt
ddcaa3d425 can.h moved from include/nuttx/ to include/nuttx/drivers. 2016-07-20 13:38:36 -06:00
Gregory Nutt
4b4dbc79a2 Move driver related prototypes out of include/nuttx/fs/fs.h and into new include/drivers/drivers.h 2016-07-20 13:15:37 -06:00
Sagitta Li
e07bd757ba STM32 F107: TIM8 not supported in F105/F107 2016-07-20 08:51:03 -06:00
Vytautas Lukenskas
ac2a5e079c Add change missing in Make.defs for last LPC43xx change 2016-07-19 09:28:15 -06:00
Vytautas Lukenskas
f222d37aa7 Extend LPC43xx EMC code to support SDRAM on a dynamic memory interface. 2016-07-19 07:11:04 -06:00
Gregory Nutt
2119c5ce19 Fix another function naming error 2016-07-18 12:40:27 -06:00
Gregory Nutt
d36da2b560 Fix bad dev[u]random_register() function return value. 2016-07-18 12:25:05 -06:00
Gregory Nutt
d5388eca05 devrandom_register() must be called before devurandom_register() 2016-07-18 11:24:04 -06:00
Gregory Nutt
078bbe5e5c All H/W RNG Drivers: Can now be configured to register as /dev/random and/or /dev/urandom 2016-07-18 11:10:37 -06:00
Gregory Nutt
1660329d06 Rename up_rnginitialize to devrandom_register 2016-07-18 10:55:37 -06:00
David Alessio
6cefbc0c3f This change provides an option to add /dev/urandom to all architectures. The pseudo-random algorithm I choose strikes an arguably-good balance between being "random" and small/fast enough for 8/16 bit MCUs. It’s the well-documented xorshift128 algorithm. It has an internal state of 128 bits that can be [re-]seeded with a write. 2016-07-17 06:42:26 -06:00
Gregory Nutt
7b298a828d up_pminitialize() needs to be called from instances of up_initialize() 2016-07-15 13:11:28 -06:00
Gregory Nutt
d3b3c71d97 All architectures: Add logic to automatically register /dev/ptmx a boot time 2016-07-15 11:54:41 -06:00
Young
7005fafb95 Fix a bug of tiva i2c ports configuration 2016-07-15 11:03:48 +08:00
Gregory Nutt
18059d6821 Restore Wolfgang Reissnegger's PR as submitted. My mistake is it late here. 2016-07-14 18:39:51 -06:00
Wolfgang Reissnegger
f982180ec7 SAM3/4 Timer: Remove broken definitions for BMR register. 
Per documentation SAM4S and SAM4E have the BMR register values
as they are already defined. No need for chip specific values.

In addition:
 - CONFIG_ARCH_CHIP_SAM4s has wrong lower case 's' so the definitions would
   not be used anyways for SAM4S builds.
 - TC_BMR_TC2XC2S_TIOA2 does not make sense. There is no way to loop back
   TC2's TIOA2 into itself.
 2016-07-14 18:17:05 -06:00
Gregory Nutt
54bc6c88dd Fix cast of return value 2016-07-14 10:21:31 -06:00
Gregory Nutt
3f6835fda9 If CONFIG_SPIFI_SECTOR512 undefined, lpc43_bwrite doesn't do actual write (probably copy/paste errors). Still not sure about current state of lpc43_spifi implementation, but for me NXFFS works with this patch. From Vytautas Lukenskas. 2016-07-14 10:11:19 -06:00
Pierre-noel Bouteville
76f12b1f69 I'm using syslog through ITM. In this case syslog_channel function is call before ram initialisation in stm32_clockconfig. But syslog channel uses a global variable that is reset to default by the RAM initialization. 2016-07-14 07:29:39 -06:00
Gregory Nutt
72582b61d9 Merged in ziggurat29/nuttx/stm32l4_smartfs_test (pull request #98) 
port foward bugfix from stm32 of oneshot timer
 2016-07-13 16:09:18 -06:00
ziggurat29
9a6c5b271a port foward bugfix from stm32 of oneshot timer 2016-07-13 17:00:06 -05:00
Gregory Nutt
37e10a54ae Kinetis: Eliminate a warning. Freedom-K64F: Update a README file 2016-07-13 15:38:47 -06:00
Gregory Nutt
beaca7a17f Merge remote-tracking branch 'origin/master' into timekeeping 2016-07-13 10:22:38 -06:00
Max Neklyudov
067f63fc18 STM32: Fix bug in oneshot timer 2016-07-13 10:20:38 -06:00
Stefan Kolb
f673b2d02a This commit solves a problem which causes data loss while sending data via USB. This problem is caused by an incorrect handling of the endpoint state in the USB driver sam_usbdevhs. This leads under some circumstances to situations in which an DMA transfer is setup while a previous DMA transfer is currently active. Amongst other things I introduced the new endpoint state USBHS_EPSTATE_SENDING_DMA for the fix. 
To reproduce the problem, I used a program which send as many data as possible via a CDC/ACM device and verified the received data on the PC.
 2016-07-13 10:09:14 -06:00
Gregory Nutt
a7d8279714 Kinetis and Freedom-K64F: Remove unused configuration variable; fix some compile issues; SDHC is now enabled in the nsh configuration (but does not work) 2016-07-13 09:56:02 -06:00
Gregory Nutt
2f12de6f28 Freedom-K64F: Add hooks for automounter; Change NSH configuration to use Windows 2016-07-13 09:23:57 -06:00
Sebastien Lorquet
590af73bd2 STM32L4 Serial: Remove some STM32Fxxx conditional logic; fix a link error resulting from an over-aggressive rename. 2016-07-13 07:10:09 -06:00
Gregory Nutt
76a0cccbb1 K6x Ethernet: Fix some conditional logic 2016-07-13 07:04:19 -06:00
Sebastien Lorquet
6be72272eb STM32L4: Apply the stm32l4 namespace and FAR qualifiers to the serial driver, also, indentation. 2016-07-12 17:18:46 -06:00
Gregory Nutt
dee77a5dd9 Kinetis Ethernet: Add support for CONFIG_NET_NOINTS 2016-07-12 16:17:35 -06:00
Gregory Nutt
10667bd38a Kinetis Ethernet and Freedcom-K64F: PHY address was wrong. Modified driver to try all PHY addresses and then only fail if the driver cannot find a usable PHY address. MDIO pin must have an internal pull-up on the Freedom-K64F. 2016-07-12 14:09:27 -06:00
Gregory Nutt
c8f053de92 Kinetis Ethernet: Add support for the KSZ8081 PHY 2016-07-12 09:59:08 -06:00
Gregory Nutt
38999dfe9d Fix two incorrectly named header files 2016-07-12 09:46:31 -06:00
Gregory Nutt
f816e7a69b Merged in slorquet/nuttx/pr_fixes (pull request #95) 
Pr_fixes
 2016-07-11 17:07:40 -06:00
Sebastien Lorquet
4172016667 revert changes made by greg 2016-07-12 01:04:15 +02:00
Sebastien Lorquet
5e12d6203e Cosmetic changes after PR 94 2016-07-12 00:57:18 +02:00
Gregory Nutt
9dd70ffbae Freedom K64F: Green and Blue LEDs reversed 2016-07-11 16:54:20 -06:00
Gregory Nutt
c80b627e8d Partial review of last PR 2016-07-11 16:28:54 -06:00
Sebastien Lorquet
749b54fbda PR fixes for oneshoot and freerun 2016-07-12 00:16:08 +02:00
Gregory Nutt
a48fb1e41c Merged in slorquet/nuttx/stm32l4_renames (pull request #94) 
stm32l4_renames
 2016-07-11 16:05:27 -06:00
Sebastien Lorquet
4f5d22c940 fix a typo 2016-07-12 00:03:38 +02:00
Sebastien Lorquet
3a873a44ef renames in USB OTG 2016-07-11 23:59:24 +02:00
Sebastien Lorquet
4dd020784a renames in tickless 2016-07-11 23:57:57 +02:00
Gregory Nutt
fb1855244e STM32 timer: Eliminate a warning 2016-07-11 13:13:17 -06:00
Sebastien Lorquet
ce09af0da7 Rename STM32L4 PWM routines. this WILL BREAK configs 2016-07-11 19:13:06 +02:00
Sebastien Lorquet
d347d7ce7e renames in oneshoot 2016-07-11 19:06:14 +02:00
Sebastien Lorquet
34a7b0ea8e Renames stm32_ -> stm32l4_ on old files and rtcc/basic timers 2016-07-11 19:05:09 +02:00
Gregory Nutt
246773faa7 Rename CONFIG_SCHED_TIMEKEEPING to CONFIG_CLOCK_TIMEKEEPING. That is a better compartmentalized name. 2016-07-11 06:54:02 -06:00
Max Neklyudov
8db29071da timekeeping: initial implementation 2016-07-10 16:14:25 -06:00