When using HSE to clock RTC NuttX internal time is gaining 5.5 second per
minute. Problem was NuttX using 7182 for one of the RTC division factors,
it should have been 7812. The incorrect factors used are 7182 and 0xff.
These are used in 3-4 places within Nuttx and other places as 7812 and 0xff.
However, the STMicro app note AN4759 suggests using 7999 and 124, which is
what I've used.
Explanation: These 2 factors are used to divide the HSE clock (which at this
point is 1 MHz) to 1 Hz for the RTC hardware.
To test the 2 factors, add 1 to both numbers and multiply them together.
The result needs to be as close as possible to 1 MHz.
The suggested values of 7999 and 124 => 8000*125 = 1,000,000, the prime
factors. So, the best fix for Nuttx would be these values.
Issue discovered and fixed by Peter Moody
since it is broken and inefficient, and then removed by:
commit dc961baaea
Author: chao.an <anchao@xiaomi.com>
Date: Thu Apr 14 18:07:14 2022 +0800
arm/armv7-[a|r]: move fpu save/restore to assembly handler
Save/Restore FPU registers in C environment is dangerous practive,
which cannot guarantee the compiler won't generate the assembly code
with float point registers, especially in interrupt handling
Signed-off-by: chao.an <anchao@xiaomi.com>
commit 8d66dbc068
Author: chao.an <anchao@xiaomi.com>
Date: Thu Apr 7 13:48:04 2022 +0800
arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only
Signed-off-by: chao.an <anchao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
by fixing filter initialization.
STM32F7 CAN3 works in single peripheral configuration and there is only 14 filter banks: 0-13. Previously not available 14 indexed filter (CAN_NFILTERS/2) was wrongly used for for receiving to FIFO. Now zero indexed filter is correctly used instead.
For FAT the same buffer is used for read and writes, there
is a possibility a cache line is dirty. But the fs is
not dirty and will not write the sector to disk. This can
be seen https://github.com/PX4/NuttX/pull/175
When the system is busy that cache line can be evicted after the
RX DMA has completed and overwrite the data in memory. The solution
is to invalidate before the DMA to prevent an evection causing an
overwite, and after the DMA it to insure coherency.
The FAT was not coherent. Resulting in a write failed
with errno:28 No space left on device.
It is unclear how the memory is acesses prior to the DMA
completion. But this restructuring ensures the data
is coherent.
This issue was not detected on the stm32h7
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
The stm32_gpiosetevent calls stm32_configgpio. So
the pin is infact restored to the SDMMC/SDIO D0.
The seconday init, dropped interrupts in a debug
build with HW stack checking on after the GPIO glich
fixes and that was how it was detected.
This prevents gliches on changing to an output mode.
If not the ALT mux can be selecting a IP block that
is drving the line to say 0. Then the output is connected
to that source, then swithced to the correct source.
Repeated automated sercon, serdis on VBUS proved to fail
for CDCACM DATA IN (device Serial TX). The root cause was
that the EP was left active after disconnect. This resulted
in the first serial write falling to kick-off the EP IN request.
That should restart the EP ISR.
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Number of configured ADC channels is currently only defined in board
level section, typically in xxx_adc.c file. This commit introduces
ioctl command ANIOC_GET_NCHANNELS that returns the number of configured
channels which is determined by the driver code. The change can allow the
applications to be more flexible when it comes to multiple ADC devices
with different number of configured channels.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
PWM drivers currently use channel number 0 for the channels that are not
used by the application. This commit adds number -1 which indicates that
all following channels are not configured and that the loop can be broken.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
it's more simple to make mm_heap_s opaque outside of mm
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5c8e435f6baba6d22b10c5f7e8d9191104fb5af2
It turns out there is no difference in these two files as well as the
reference manual for the registers between the two parts, so it probably
makes sense to unify them
since kernel component should use UTC instead local time
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Icf939e1ab0af8e577105f539d2553bc67b3b3d10
Sebastien Lorquet has submitted the CLA
Uros Platise has submitted the CLA
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Drop to user-space in kernel/protected build with up_pthread_exit,
now all pthread_cleanup functions executed in user mode.
* A new syscall SYS_pthread_exit added
* A new tcb flag TCB_FLAG_CANCEL_DOING added
* up_pthread_exit implemented for riscv/arm arch
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
stm32f7:SDMMC Use inttypes in printing macro
stm32f7:CAN Use inttypes in printing macro
stm32f7:DMA Use inttypes in printing macro
stm32f7:serial fix compile error from UNUSED() change
Change the logic for allocating user heap for PROTECTED_BUILD:
- Don't rely on SRAM1_END alignment
- Make better use of MPU subregions when allocating the heap
- Don't duplicate the calculation of user heap start in kernel heap
allocation; use the previous calculation directly
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
All supported arch uses a push-down stack:
The stack grows toward lower addresses in memory. The stack pointer
register points to the lowest, valid working address (the "top" of
the stack). Items on the stack are referenced as positive(include zero)
word offsets from sp.
Which means that for stack in the [begin, begin + size):
1.The initial SP point to begin + size
2.push equals sub and then store
3.pop equals load and then add
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Ken Pettit has submitted the ICLA and we can migrate the licenses
to Apache.
Sebastien Lorquet has submitted the ICLA and we can migrate the licenses
to Apache.
Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Marco Krahl has submitted the ICLA and we can migrate the licenses
to Apache.
Gregory Nutt, S.A has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
