Squashed commit of the following:
arch/arm/src/lpc43xx: SDMMC driver now builds for the LPC43 (provided that the proper definitions appear in the board.h file).
arch/arm/src/lpc43xx: Update basic changes to the ported lpc54xx driver for lpc43xx clocking and GPIOs.
arch/arm/src/lpc43xx: Brings in the LPC54xx SD/MMC driver with absolutely no changes other than changing all occurences of 54 to 43.
arm/arm/src/lpc43xx: Add build support for the lpc54 SDMMC driver.
lpc54 SDMMC: Check for successful data transfer last. Checking first means that we miss errors.
Squashed commit of the following:
arch/arm/src/lpc54xx: SDMMC fixes.. DMA should not be enabled on non-DMA transfers, the burst setting in FIFOTH is supposed to match the burst setting in the BMOD reseters, Add DMA error interrupt support.
arch/arm/src/lpc54xx: Mostly costmetic changes to the SDMMC driver.
In lc823450, ldrex and strex are not supported. So we implemented
up_testset() with H/W Mutex. However, there was a bug in memory
access order. This change ensures correct memory access order in
up_testset() for lc823450.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
lc823450 http streaming
* arch/arm/src/lc823450: Use spinlock APIs in lc823450_gpio.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add a warning message in up_ack_irq()
In SMP mode, H/W interrupts should be handled on CPU0 to avoid deadlocks.
Other changes:
Fix a potential race condition in up_enable_irq()
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Enable HRT_TIMER in lc823450_timerisr.c
Other changes:
Fix style violations and call up_enable_irq() to assign CPU0 for IRQ handling.
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix race conditions in dma/usbdev.
In SMP mode, critical data must be protected explicitly.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt
Add notes on .gdbinit and networking. Update comments on SMP.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update defconfigs
Enable HRT_TIMER, LC823450_MTM0_TICK, SPINLOCK_IRQ
Enable NET_TCP_RWND_CONTROL, NXPLAYER_HTTP_STREAMING_SUPPORT (rndis only)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/lpc54xx: Adds the LPC54-specific clock configuration logic to the leveraged SD/MMC driver.
arch/arm/src/lpc54xx: Leveraged SD/MMC driver builds without error but is still missing clock configuration logic.
arch/arm/src/lpc54xx: Bring in LPC43xx SD/MMC driver from https://github.com/Smoothieware/smoothie-nuttx/tree/master/nuttx/arch/arm/src/lpc43xx
arch/arm/src/lpc54xx: LCD.. Fix some miconceptions about how the video address lines are used.
arch/arm/src/lpc54xx: Fix some LCD BPP and BRG vs RGB settings.
lc823450 smp improvement
* arch/arm/src/common: Apply irq_spin APIs to modifyregXX
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.
Please see 6150299f54 as well.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Do not use modifyreg32() to enable Mutex.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Modify IRQ control for i2s
Interrupt will be handled on CPU0 with this change.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Apply irq_spin APIs to dma/syscontrol/usbdev.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Assign CPU1 to lpwork
This change will improve load balancing for networking with RNDIS.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* drivers/audio/wm8776.c: Improve stability in SMP mode
Apply irq_spin APIs to improbe performance.
Repeat to process a message to avoid deadlock.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Enable SPINLOCK_IRQ and NXPLAYER in rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/lpc54xx: Finish off some missing logic. Complete now execpt for GPIO and LED support.
arch/arm/src/lpc54xx: Add lpc54_clrpend.c
arch/arm/src/lpc54xx: Serial driver is complete and compiles.
arch/arm/src/lpc54xx: Add beginning of a serial driver (still missing some logic)
arch/arm/src/lpc54xx: Fleshes out low level USART intialization.
arch/arm/src/lpc546xx/Kconfig: Add hooks to integrate with common seril upper half.
arch/arm/src/lpc54xx: Beginning of USART console support.
arch/arm/src/lpc54xx: Completes very basic clock configuration.
arch/arm/src/lpc54xx: Add clocking logic (still not complete)
arch/arm/src/lpc54xx: Beginning of PLL configuration logic.
arch/arm/src/lpc54xx: Fix a few things from first compile attempt. Compilation cannot work until I at least finish the clock configuration logic.
arch/arm/src/lpc54xx: Addes some SysTick logic.
arch/arm/src/lpc54xx: Completes basic startup logic (sans clock configuration) and interrupt configuration.
arch/arm/src/lpc54xx: Add generic ARMv7-M start-up logic (needs LPC54628 customizations); add emtpy file that will eventually hold the clock configuration logic.
arch/arm/src/lpc54xx: Add (incomplete) SYSCON register definition header file.
arch/arm/src/lpc54xx: Add FLEXCOMM header file.
arch/arm/src/lpc54xx: Bring in tickless clock logic from LPC43; configs/lpcxpresso-lpc54628: mount procfs if enabled.
arch/arm/src/lpc54xx: Add RIT clock definitions; add SysTick initialization (not finished)
LPC54xx and LPCXpresso-LPC54628: add more boilerplate files and stubbed out files.
arch/arm/src/lpc54xx: Add (incomplete) USART header file.
Add another condition to a Kconfig; refresh a defconfig.
arch/arm/src/lpc54xx/chip: Add LPC54628 memory map header files.
configs/lpcxpresso-lpc54628: Add basic build files for the LPCXpresso-LPC54628
arch/: Basic build directory structure for the LPC54628
arch/arm/src/xmc4/Kconfig: Define user friend I2C alias to follow other arch names
arch/arm/src/xmc4/Kconfig: Define user friend LIN alias to follow other arch names
arch/arm/src/xmc4/Kconfig: Define user friend I2S alias to follow other arch names
lc823450 smp audio
* arch/arm/src/lc823450: Remove a workaround in up_cpu_paused()
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Introduce g_gpio_lock to improve write performance in SMP mode.
NOTE: This is a tentative solution and should be replaced with more generic one.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add a workaround in up_txready() to avoid data corruption.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Enable CONFIG_SMP for audio
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt regarding SMP audio
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
1) The first enables building with CONFIG_ARCH_IDLE_CUSTOM enabled.
2) The second allows changing voltage output scaling setting and prevents enabling over-drive mode for low frequencies (STM32 F74xx, 75xx, 76xx, 77xx)
STM32, STM32 L4, and STM32 M4: USB OTGFS DMA trace output fix
STM32: Add dump buffer feature to stm32 F4 series
STM32 and STM32 L4: Fix bad USB OTGFS register address
STM32 L4: Fix typo in USB OTGFS register usage
STM32 L4: Add check in USB OTGFS driver to assure that SYSCFG is enabled
Nucleo-L496ZG: Make HSE on Nucleo-L496ZG default to enable USB
lc823450 auto LED support
* arch/arm/src/lc823450: Add auto LED for CPU activity
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Add auto LED support
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
configs/stm32f429i-disco/ltdc: This configuration has been deleted because it violated the portable POSIX OS interface. It used apps/examples/ltdc and include ltdc.h and dma2d.h which were also removed for the same reason.
Fix stm32 dmacapable on f20xx
* Fixed build for STM32F20XX platforms when CONFIG_STM32_DMACAPABLE is enabled
* Fixed build for STM32F20XX platforms when CONFIG_STM32_DMACAPABLE is enabled
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Port STM32F7 I2C driver to STM32L4
* arch/stm32l4: port STM32F7 I2C driver to STM32L4
STM32L4 I2C driver is in work-in-progress state (plentiful of
TODOs and #warnings) and lags many features found in more
up-to-date STM32 I2C drivers. The peripheral on STM32F7 and
STM32L4 are identical except for L4's 'wakeup from stop mode'
flag and STM32F7's I2C driver is in more 'ready to use' state.
Patch ports the STM32F7 I2C driver to STM32L4. The I2C clock
configuration is kept the same as before (I2CCLK = PCLK1 80 Mhz)
instead of switching to STM32F7 arch default that is I2CCLK=HSI.
Further work would be to add configuration option for choosing
I2C clock source instead of current hard-coded default.
* arch/arm/stm32f7: i2c: restore bus frequency after I2C reset
Copy frequency restoration fix from STM32L4 I2C driver to STM32F7 I2C driver.
* arch/arm/stm32f7: i2c: remove unused Kconfig option
* configs/nucleo-l496zg/nsh: enable I2C4 bus with i2ctool
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* stm32_hrtim: fix warnings related with RCC
* stm32f33xxx_adc: add some publicly visable interfaces and some code to support injected channels
* stm32f33xxx_dma: add public interface to handle with DMA interrupts
* stm32_hrtim: change some names and add some coments
* chip/stm32f33xxx_adc.h: cosmetics
* nucleo-f334r8: add logic for zero latency high priority interrupts example
* stm32: update some ADC-related configuration in Kconfig
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32L1, STM32L4 RTC: add periodic interrupts, update L1 RTC implementation
* STM32L4 RTC: add support experimental CONFIG_RTC_PERIODIC
* STM32 RTC: separate STM32L1 RTC into a separate file
STM32L1 RTC is very close to F4 or L4 versions, with two alarms
and periodic wakeup support so backported L4 peripheral to L1.
* RTC: add periodic alarms to upper and lower halves
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* stm32f33xxx_adc.c: fix some warnings and compilation error when extsel not in use
* nucleo-f334r8/adc: change serial console to USART2 (STLINK COM)
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Lower part of STM32 CAN driver arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and clears TXFP bit in the CAN_MCR register (it means transmission order is defined by identifier and mailbox number).
This creates situation when order frames are put in upper part of CAN driver (via can_write) and order frames are sent on bus can be different (and I experience this in wild).
Since CAN driver API pretends to be "file like" I expect data to be read from fd the same order it is written. So I consider described behaviour to be a bug.
I propose either to set TXFP bit in the CAN_MCR register (FIFO transmit order) or to use only one mailbox.
