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445 Commits

Author SHA1 Message Date
Gregory Nutt
3ddea73dc1 arch/arm/src/armv7-a: Port the SMP change by Masayuki Ishikawa to the ARMv7-A family. 2018-02-14 08:36:34 -06:00
Gregory Nutt
de34b4523f sched/ and arch/arm/src/armv7-a: Replace a few more occurrences of this_task() with current_task(cpu) in an effort to get the i.MX6 working in SMP mode again. It does not yet work, sadly. 2018-02-06 11:17:33 -06:00
Gregory Nutt
8aa1538506 arch/arm/src/armv7-a: Found some additional places were the new this_task() function cannot be called in the i.MX6 SMP configuration. 2018-02-06 10:33:28 -06:00
Gregory Nutt
5c5d19f1c8 Some ommissions from previous commit. 2018-02-04 12:36:51 -06:00
Gregory Nutt
1e59d9dd14 armv7-a, armv7-r, armv7-m: Add atomic read-add-write and read-subtract-write functions. 2018-02-04 12:22:03 -06:00
Gregory Nutt
2683f713ab Make sure that labeling is used consistently in all function headers (part 3). 2018-02-01 12:17:03 -06:00
Gregory Nutt
1567b82429 Make sure that labeling is used consistently in all function headers (part 2). 2018-02-01 12:03:55 -06:00
Gregory Nutt
7cf88d7dbd Make sure that labeling is used consistently in all function headers. 2018-02-01 10:00:02 -06:00
Gregory Nutt
1c5ec07414 arch/: Remove dangling space at the end of lines. 2017-06-28 13:16:48 -06:00
Gregory Nutt
6e4918c557 Remove CONFIG_ARM_TOOLCHAIN_GNU; replace with CONFIG_ARCH_TOOLCHAIN_GNU 2017-05-13 13:28:15 -06:00
Gregory Nutt
0de294a586 Fix lots of occurrences of 'the the', 'the there', 'the these', 'the then', 'the they. 2017-05-11 13:35:56 -06:00
Mark Schulte
b3222bbc8a irq_dispatch: Add argument pointer to irq_dispatch 
Provide a user defined callback context for irq's, such that when
registering a callback users can provide a pointer that will get
passed back when the isr is called.
 2017-02-27 06:27:56 -06:00
Gregory Nutt
ff61d8f69d Add missing sched_note_*() calls to sam4cm SMP functions. 2017-01-24 14:33:57 -06:00
Gregory Nutt
edd9186540 ELF: Move ARMv7-A and ARMv7-R versions of ELF relocation logic to libc/machine 2017-01-21 14:40:26 -06:00
Gregory Nutt
be5ba90d4f Move optimized ARM memcpy functions from arch/arm/src/ to libc/machine/. This is necessary for the PROTECTED and KERNEL build modes. Otherwise, memcpy() will be built in to kernel space and not accessible to applications. 2017-01-20 10:53:46 -06:00
Gregory Nutt
0db31d0cd1 SMP: Fix a typo introduced in c5b00ccfc4 2017-01-16 08:48:05 -06:00
Gregory Nutt
a2083fbc92 Update some comments 2017-01-15 12:35:03 -06:00
Gregory Nutt
2837eff0cd SMP: Most cosmetic clean-up from review of previous commit. 2017-01-14 09:22:13 -06:00
Gregory Nutt
c5b00ccfc4 SMP Signals: Fix some SMP signal delivery logic. Was not handling some critical sections correctly and was missing logic to signal tasks running on other CPUs. 2017-01-14 08:28:37 -06:00
Gregory Nutt
13d00344c9 Add configuration to prevent selection of Windows native toolchains when using Ubuntu under Windows 10 2017-01-02 07:16:47 -06:00
Gregory Nutt
3a0413c048 Back out most of 34be3e7c3c and update README again. Windows native tools cannot be used with Ubuntu under Windows 10 now. For Cygwin, that support depends on the 'cygpath -w' tool to convert POSIX paths to Windows paths. There is no corresponding tool for Ubuntu under Windows 10. 2017-01-01 16:29:03 -06:00
Gregory Nutt
34be3e7c3c Add configuration support for builds with Ubuntu under Windows 10 2017-01-01 15:34:23 -06:00
Gregory Nutt
49fae0ac6b Revert "All CMP platforms: Apply same fix verified on other platforms found on Xtensa." 
This reverts commit fb146abee0.
 2016-12-25 07:08:44 -06:00
Gregory Nutt
efb86382c3 SMP: Back out deferred IRQ locking. This was accidentally merged into master and it looks like it is going to be more work than I thought to get it working again. Changes will go to the irqlock branch. 2016-12-24 19:53:37 -06:00
Gregory Nutt
729ee7c099 ARMv7-A: Small improvement to some register handling in context restoration. 2016-12-23 11:13:18 -06:00
Gregory Nutt
d9ef0e86fb Fix a couple of errors in the last commit 2016-12-23 10:45:13 -06:00
Gregory Nutt
c00a1870d7 Implement deferred IRQ locking. Adds support for ARMv7-A. 2016-12-23 10:17:36 -06:00
Gregory Nutt
fb146abee0 All CMP platforms: Apply same fix verified on other platforms found on Xtensa. 2016-12-21 14:04:09 -06:00
Gregory Nutt
26560cb9e1 i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept. 2016-12-13 16:59:50 -06:00
Gregory Nutt
edeee90c66 i.MX6 interrupt handling: Additional logic needed to handle nested interrupts when an interrupt stack is used 2016-12-13 10:04:38 -06:00
Gregory Nutt
a7b688e87b sched notes: Add additional note to see if/when CPU is started in SMP mode. 2016-12-07 09:08:20 -06:00
Gregory Nutt
dc79e35d65 For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and cache broadcasts. Does not fix SMP cache problem. 2016-12-07 09:06:41 -06:00
Gregory Nutt
f06d521c10 Minor extensions to some comments 2016-11-29 10:01:38 -06:00
Gregory Nutt
79bb895073 i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set. 2016-11-29 08:34:22 -06:00
Gregory Nutt
a8b69c3efe Back out a debug change that was included in commit 2016-11-29 07:51:49 -06:00
Marc Rechté
3f91bd6056 STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence, up to three interfaces. 2016-11-29 07:03:54 -06:00
Gregory Nutt
d65be718c2 sched_note: Extend OS instrumentation to include some SMP events. 2016-11-27 17:14:57 -06:00
Gregory Nutt
cbf98ae0a0 ARMv7 GIC: SGIs are non-maskable but go through the same path as other, maskable interrupts. Added logic to serialize SGI processing when necessary. 2016-11-27 13:18:34 -06:00
Gregory Nutt
21e42d18c1 ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in initialization of CPUn, n>0 2016-11-27 11:28:24 -06:00
Gregory Nutt
cd54c71dc1 ARMv7-A/i.MX6: Modify handling of the SMP cache coherency configuration so that it is identical to the steps from the TRM. Makes no differenct, however. 2016-11-27 10:21:46 -06:00
Gregory Nutt
278d8330d6 arm_scu.c edited online with Bitbucket. Fux some typos. 2016-11-27 02:59:42 +00:00
Gregory Nutt
3f6eadc238 ARMv7-A: Fix some SCU SMP logic 2016-11-26 18:41:48 -06:00
Gregory Nutt
546e352830 i.MX6: Add some controls to enable SMP cache coherency in SMP mode 2016-11-26 17:46:20 -06:00
Gregory Nutt
3353d9280f i.MX6: Disable non-cached region support. Add SCU register definitions. 2016-11-26 17:03:57 -06:00
Gregory Nutt
b2ba12e02a SMP: Basic function 2016-11-26 14:23:23 -06:00
Gregory Nutt
785ed5faf2 SMP: A few more compile/link issues. Still problems. 2016-11-26 13:20:11 -06:00
Gregory Nutt
aae306e942 i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. 2016-11-26 12:04:02 -06:00
Gregory Nutt
e3fe320e08 SMP: Add support for linking spinlocks into a special, non-cached memory region. 2016-11-26 08:47:03 -06:00
Gregory Nutt
b08fb33c28 SMP: Fix typos in some conditional compilation 2016-11-24 17:59:45 -06:00
Gregory Nutt
7f636f2280 SMP: Add spin_trylock(). Use this in conditions where other CPUs need to stopped but we cannot call enter_critical_section. 2016-11-24 13:33:43 -06:00
Gregory Nutt
f77dcdf323 ARMv7-A SMP: Add a little logic to signal handling. 2016-11-24 11:45:05 -06:00
Gregory Nutt
c03d126da6 arm_cpupause.c edited online with Bitbucke. What was I thinking... Back out previous change. 2016-11-24 04:45:07 +00:00
Gregory Nutt
19e7f2210e arm_cpupause.c edited online with Bitbucket. Fix a typo in a comment. 2016-11-24 04:24:40 +00:00
Gregory Nutt
4b0bbf41ca SMP: Fix backward condition in test. 2016-11-23 22:24:14 -06:00
Gregory Nutt
f90525a5d1 SMP: Update some comments; trivial improvement by inlining static function. 2016-11-22 16:48:57 -06:00
Gregory Nutt
bac7153609 SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused 2016-11-22 11:34:16 -06:00
Gregory Nutt
130bfa3f6b Remove a assertion condition that appears to rarely cause false-alarm assertions. Teported by Petteri Aimonen 2016-11-21 14:43:56 -06:00
Gregory Nutt
bb19f1b499 spinlocks should be volatile. 2016-11-17 10:04:22 -06:00
Gregory Nutt
841e1aa77f Fix a cloned typo 2016-10-19 09:14:21 -06:00
Gregory Nutt
7f16548f57 Replaces last three commits. Does the same thing, but does it in a way that does not change the usage model. 2016-06-21 05:26:08 -06:00
Gregory Nutt
c05da80a27 Eliminate a warning 2016-06-20 22:54:58 -06:00
Gregory Nutt
505ca542e8 Remove some last traces of lowvsyslog that were missed; Add a SYSLOG emergency channel for handling assertion output more cleanly 2016-06-20 16:11:50 -06:00
Gregory Nutt
43eb04bb8f Without lowsyslog() *llinfo() is not useful. Eliminate and replace with *info(). 2016-06-20 11:59:15 -06:00
Gregory Nutt
15c260a428 armv7-a/armv6-m/arm/a1x: Convert *err() to either *info() or add ERROR:, depending on if an error is reported 2016-06-17 16:44:50 -06:00
Gregory Nutt
b39e53391d Add underscore at beginning of alert() as well 2016-06-16 12:38:05 -06:00
Gregory Nutt
0c8c7fecf0 Add _ to the beginning of all debug macros to avoid name collisions 2016-06-16 12:33:32 -06:00
Gregory Nutt
6f08216621 Centralize definitions associated with CONFIG_DEBUG_SYSCALL 2016-06-16 08:12:38 -06:00
Gregory Nutt
c4e6f50eac Centralize definitions associated with CONFIG_DEBUG_IRQ 2016-06-15 08:35:22 -06:00
Gregory Nutt
a98bc05f65 New debug macro: alert(). This is high priority, unconditional output and is used to simplify and stanardize crash error reporting. 2016-06-14 09:07:53 -06:00
Gregory Nutt
0f249016a0 Eliminate some warnings 2016-06-13 14:01:32 -06:00
Gregory Nutt
be80a0b99c Eliminate some warnings 2016-06-11 16:40:53 -06:00
Gregory Nutt
a1469a3e95 Add CONFIG_DEBUG_ERROR. Change names of *dbg() * *err() 2016-06-11 15:50:49 -06:00
Gregory Nutt
e99301d7c2 Rename *lldbg to *llerr 2016-06-11 14:55:27 -06:00
Gregory Nutt
1cdc746726 Rename CONFIG_DEBUG to CONFIG_DEBUG_FEATURES 2016-06-11 14:14:08 -06:00
Gregory Nutt
fc3540cffe Replace all occurrences of vdbg with vinfo 2016-06-11 11:59:51 -06:00
Gregory Nutt
3a74a438d9 Rename CONFIG_DEBUG_VERBOSE to CONFIG_DEBUG_INFO 2016-06-11 11:50:18 -06:00
Gregory Nutt
80d0b2736e Reorder some logic: (1) set initial CPU IDLE task regsters AFTER allocating stack, (2) invalidate cache in CPU start-up BEFORE handling first interrupt. 2016-05-22 15:01:49 -06:00
Gregory Nutt
356692d70e SMP: Need to enable FPU on other CPUs as well 2016-05-20 13:35:58 -06:00
Gregory Nutt
07acd5327a SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started. 2016-05-20 12:39:02 -06:00
Gregory Nutt
f454b38d6e ARMv7-A SMP: Allow CONFIG_SMP_NCPUS=1 for testing purposes 2016-05-18 09:17:02 -06:00
Gregory Nutt
e6728bac29 Cortex-A9 GIC: Add an interface to set interrupt edge/level trigger 2016-05-16 14:42:55 -06:00
Gregory Nutt
4feeb0c2b4 Cortex-A9 GIC: Some fixes that I don't fully understand but do indeed give me serial interrupts 2016-05-16 12:50:35 -06:00
Gregory Nutt
a3f3cc12c0 Update some comments; Fix grammatic error in ChangeLog. 2016-05-13 17:36:08 -06:00
Gregory Nutt
faca2fb1e7 ARMv7-A/i.MX6: Add logic to handle allocation of CPU IDLE thread stacks more efficiently 2016-05-13 11:39:42 -06:00
Gregory Nutt
d14d84c1a6 ARMv7M/i.MX6: Implement CPUn n=1,2,3 startup logic 2016-05-13 09:11:55 -06:00
Gregory Nutt
70782b0f14 ARMv7-A i.MX6: More SMP logic. Still untested. 2016-05-12 15:04:46 -06:00
Gregory Nutt
99e695398c Rename up_boot to arm_boot 2016-05-12 13:42:49 -06:00
Gregory Nutt
26ba3a2b96 Cosmetic changes from review of last PR 2016-04-18 06:50:45 -06:00
Gregory Nutt
84b399136e GIC: Level or edge sensitive interrupt? 2016-04-01 13:26:57 -06:00
Gregory Nutt
f698f3dcbe ARMv7-A GIC: Fix another initialization errors 2016-04-01 08:53:43 -06:00
Gregory Nutt
ddc1b88027 ARMv7-A GIC: Fix some initialization errors 2016-04-01 08:40:51 -06:00
Gregory Nutt
855c9a5225 ARMv7-A GIC: Move debug logic to a separate file; fix some errors in debug logic. 2016-04-01 06:58:49 -06:00
Gregory Nutt
37cacc6178 ARMv7 GIC: Fix some formatting errors in GIC debug output 2016-03-31 18:26:15 -06:00
Gregory Nutt
70683d08bc i.MX6: Add GIC debug output 2016-03-31 17:25:04 -06:00
Gregory Nutt
756e6050e4 ARMv7-A: Need to set bits in the ICDDCR to enable forwarding of interrupts 2016-03-31 09:18:55 -06:00
Gregory Nutt
12064b276a ARMv7-A: Fix an error in GIC initialization 2016-03-31 08:05:12 -06:00
Gregory Nutt
1c56b8dd87 Update some ARM registers for Cortex-A9 2016-03-29 11:47:35 -06:00
Gregory Nutt
dcc93a7a44 Make it clear that GIC support is GICv2 2016-03-14 10:50:54 -06:00
Gregory Nutt
41b3af52b7 i.MX6: Revamp GIC initialization logic; add missing register bit definitions and initialization of GIC control register for secure cases 2016-03-13 10:12:45 -06:00
Gregory Nutt
6288e381ee Conform to revised SMP interfaces. Improve i.MX6 SMP startup handshake. 2016-03-12 15:22:45 -06:00
Gregory Nutt
8ad1188fe5 i.MX6: Finish initial cut at all SMP support 2016-03-12 13:23:49 -06:00
Gregory Nutt
cbe7321508 i.MX6: Finish GIC initialization 2016-03-12 11:38:16 -06:00
Gregory Nutt
4d484399a9 ARM: Remove some obsolete and incorrect conditional compilation 2016-03-11 12:42:58 -06:00
Gregory Nutt
87e7e135ba i.MX6: GIC decode and prioritization logic 2016-03-11 09:49:00 -06:00
Gregory Nutt
bc0fb5453a i.MX6: A little more GIC initialization logic 2016-03-11 09:00:49 -06:00
Gregory Nutt
3d6519a223 Implement Cortex-A9 up_cpu_index() using the MPIDR register. Thanks Alan. 2016-03-10 14:02:58 -06:00
Gregory Nutt
a94febb551 MPCore: Fix missing header file inclusion; Add GIC-based implementations of up_enabable_irq(0 and up_disable_irq() 2016-03-10 08:37:34 -06:00
Gregory Nutt
5c75f83b55 ARMv7-A GIC: Add definitions for shared interrupt IDs 2016-03-10 07:13:40 -06:00
Gregory Nutt
4d4f54a789 Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs 2016-03-09 13:41:48 -06:00
Gregory Nutt
7b0a696498 i.MX6: Add a system timer based on the i.MX6 GPT 2016-03-09 12:16:44 -06:00
Gregory Nutt
80dce6dba1 i.MX6: Add incomplete GPT header file 2016-03-09 09:08:01 -06:00
Gregory Nutt
613786ff3d ARMv7-A: Add global timer header file 2016-03-09 08:36:22 -06:00
Gregory Nutt
c404eae718 Costmetic update to comments 2016-03-03 09:12:13 -06:00
Gregory Nutt
3a14a4c4c6 i.MX6: Put in basic framework for interrupt handling 2016-03-03 08:50:56 -06:00
Gregory Nutt
a0783791a9 GIC: Fix some name collisions and naming inconsistencies 2016-03-03 08:50:25 -06:00
Gregory Nutt
52d499ba33 ARMv7-A: Add hooks for some common GIC logic 2016-03-02 14:56:54 -06:00
Gregory Nutt
db331d47dd ARMv7-A: Clean up some kruft in gic.h 2016-03-01 12:55:48 -06:00
Gregory Nutt
f2eb90cd1c i.MX6: Add definition of base address of ARM multi-core registers 2016-03-01 08:26:30 -06:00
Gregory Nutt
6949ff553b ARMv7-A: Revamp gic.h. Add mpcore.h 2016-03-01 08:21:26 -06:00
Gregory Nutt
bb62237c80 ARMv7-A: gic.h: Use register names from MPCore spec 2016-02-29 19:25:59 -06:00
Gregory Nutt
1fdc8db30c ARMv7-A: Add GIC register definition header file 2016-02-29 18:13:51 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
70e502adb0 Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section() 2016-02-13 19:11:09 -06:00
Gregory Nutt
a6eb9a351c Add spinlock support for ARMv7-M architectures 2016-02-09 13:44:22 -06:00
Gregory Nutt
5d449e9991 Add spinlock support for ARMv7-A architectures 2016-02-09 12:53:10 -06:00
Gregory Nutt
ed4e3c0a9e ARM: Replace explicit references to g_readytorun with indirect references via the macro this_task() 2016-02-06 13:41:28 -06:00
Gregory Nutt
10001f8556 WINTOOl should be selected only for Cygwin. MSYS and native should not have it. 2016-01-09 16:34:33 -06:00
Gregory Nutt
6d0650349a Add support for ARM big-endian toolchains with prefix armeb- 2015-12-26 18:13:01 -06:00
Gregory Nutt
9bcf27d15b TMS570 is big-endian 2015-12-26 14:47:54 -06:00
Gregory Nutt
092c681157 TMS570: Add a little more IRQ/FIQ logic 2015-12-21 10:57:01 -06:00
Gregory Nutt
63d5032d3b TMS4570: Was not building arm_head.S or up_allocateheap.c; ARMv7-R: Fix variious problems not that arm_head.S is being built 2015-12-19 18:56:23 -06:00
Gregory Nutt
bacf7cf07e ARMv7-R: fix some issues to get a clean compilation; TMS570: Add enough logic to support a minimum build. Not much there on the initial commit 2015-12-16 09:03:14 -06:00
Gregory Nutt
1f05f49e66 ARMv7-A: Update some co-processor register naming 2015-12-14 13:04:03 -06:00
Gregory Nutt
6e9aa0a1d7 ARMv7-A/M: Cosmetic changes 2015-12-14 11:56:39 -06:00
Gregory Nutt
edecfc2dac ARMv7-A: Cosmetic changes 2015-12-14 08:42:39 -06:00
Gregory Nutt
daea1e614b All architectures need to build ELF support if either CONFIG_ELF or CONFIG_MODULE are selected. Cortex-M7 also must support module cache corherence 2015-12-12 09:35:05 -06:00
Gregory Nutt
79df561669 Rename board_led_off to board_autoled_off 2015-11-01 09:09:36 -06:00
Gregory Nutt
b28e32e3d3 Rename board_led_on to board_autoled_on 2015-11-01 09:07:06 -06:00
Gregory Nutt
b6638315a4 Correct some spacing issues 2015-10-07 11:39:06 -06:00
Gregory Nutt
0ca999e119 Make some spacing comply better with coding standard 2015-10-06 16:23:32 -06:00
Gregory Nutt
3fdd914203 Costmetic fixes to C coding style 2015-10-05 17:13:53 -06:00
Gregory Nutt
6fc6d17760 Fix some spacing problems 2015-10-04 14:59:08 -06:00
Gregory Nutt
cae0c9a2e3 Standardize the width of all comment boxes in header files 2015-10-02 17:47:23 -06:00
Gregory Nutt
36726b1bc4 Standardize the width of all comment boxes in header files 2015-10-02 17:42:29 -06:00
Gregory Nutt
26347891ac Apply same fix for ARMv7-M to other architectures 2015-09-30 11:21:04 -06:00
Gregory Nutt
70f1a49fbe arch/arm/src/up_iternal.h and several ARM Make.defs files: In the original implementation, NOT defined(CONFIG_ARMV7M_CMNVECTOR) was a sufficient test to determine if lazy floating point register saving was being used. But recents changes added common lazy register as well so now that test must be (NOT defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU)). 2015-08-31 08:40:02 -06:00
Gregory Nutt
0843af5367 Fixes that call sched_resume_scheduler and sched_suspend_scheduler must include nuttx/sched.h 2015-07-29 16:51:26 -06:00
Gregory Nutt
eddf8161a5 Add scheduler resume/suspend calls to all implementations of up_release_pending() 2015-07-26 10:13:29 -06:00
Gregory Nutt
37969b8279 Add scheduler resume/suspend calls to all implementations of up_reprioritize_rtr() 2015-07-26 09:46:28 -06:00
Gregory Nutt
838c5355eb Correct resume scheduler hooks and add suspend scheduler hooks to all implementations of up_unblock_task 2015-07-26 09:07:47 -06:00