Commit Graph

21381 Commits

Author SHA1 Message Date
chenwen@espressif.com
75999d247f xtensa/esp32s3: SPI support psram and flash timing tuning
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-09-15 00:35:17 +08:00
Peter van der Perk
0d4b42255b s32k3: emac use semi-unique MAC address 2023-09-14 20:54:21 +08:00
simbit18
50e6dcb1e0 Fix nuttx coding style
Correct forming guard names
2023-09-13 22:49:38 +08:00
simbit18
b3973496cd Fix Kconfig style
Remove spaces from Kconfig
Add comments
2023-09-13 21:39:49 +08:00
wangming9
72cf51faf3 arm/psci: Fixed arm psci related compilation errors
Summary
include/arch/syscall.h: Assembler messages:
include/arch/syscall.h:133: Error: bad instruction `struct arm_smccc_res'
include/arch/syscall.h:134: Error: junk at end of line, first unrecognized character is `{'
include/arch/syscall.h:135: Error: bad instruction `unsigned long a0'
include/arch/syscall.h:136: Error: bad instruction `unsigned long a1'
include/arch/syscall.h:137: Error: bad instruction `unsigned long a2'
include/arch/syscall.h:138: Error: bad instruction `unsigned long a3'
include/arch/syscall.h:139: Error: bad instruction `unsigned long a4'
include/arch/syscall.h:140: Error: bad instruction `unsigned long a5'
include/arch/syscall.h:141: Error: bad instruction `unsigned long a6'
include/arch/syscall.h:142: Error: bad instruction `unsigned long a7'
include/arch/syscall.h:143: Error: junk at end of line, first unrecognized character is `}'
include/arch/syscall.h:145: Error: bad instruction `typedef struct arm_smccc_res

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-09-13 21:06:51 +08:00
Jukka Laitinen
bd52ae1ad9 arch/risc-v/src/mpfs/mpfs_i2c.c: Clean up using priv->status and STOP interrupts
- There are occasional extra STOPs being sent due to an IP bug when using an
  FPGA based I2C. Add a flag "inflight" to mask out extra STOP interrupts when
  using the FPGA based implementation
- There are no MPFS_I2C_ST_STOP_SENT irq's "initally". It is just already
  either success or still in progress

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-09-12 22:11:24 +08:00
jianglianfang
479bfd5414 sim_framebuffer: add double buffer for sim
support double framebuffer mode and adapter to the new vsync queue.

Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2023-09-12 22:10:10 +08:00
pengyiqiang
6536ddcdcf sim/framebuffer: remove duplicate poll notify
The framebuffer of the emulator is a single buffer mode, and the pan_display method is not implemented, so as long as the fb device is created and poll notify once, the fb can be kept in a writable state.

Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
2023-09-12 22:10:10 +08:00
Shanmin Zhang
b9fb9bea1d arm: support reboot / poweroff for qemu virt arm
Signed-off-by: Shanmin Zhang <zhangshanmin@xiaomi.com>
2023-09-12 21:57:13 +08:00
Tomáš Pilný
98b43752d5 esp32/rmt: fix bug in rmt_reset 2023-09-12 17:44:42 +08:00
Tomáš Pilný
103270be1d esp32/rmt: Improve comments in ESP32's RMT peripheral 2023-09-12 17:44:42 +08:00
Xiang Xiao
d4fd9f53cd Fix error: arch/sim/src/sim/posix/sim_alsa.c:290:18: error: 'flags' undeclared
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-12 10:02:50 +08:00
daniellizewski
a75b3bad15 Fixed typo in CRC define 2023-09-12 00:41:59 +08:00
Petro Karashchenko
a003a7ea36 arch/xtensa/esp32s3: add UART RS485 support
This commit adds support of RS485 support in ESP32-S3 serial driver

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-11 23:20:49 +08:00
Pavel Pisa
b9472129c8 arch/arm/samv7: fix typos in quadrature encoder and timer drivers
The typo s/.timid/.tcid prevents to compile NuttX with
quadrature encoder configured for timer1 (CONFIG_SAMV7_TC1_QE)
and s/SAM_TC789_BASE/SAM_TC678_BASE prevented use of the
of the timer 2.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
2023-09-11 23:11:43 +08:00
yintao
9e43a4d31c sim: To avoid system calls being interrupted when use host api
Signed-off-by: yintao <yintao@xiaomi.com>
2023-09-11 20:33:49 +08:00
hujun5
70a67099b3 timer/trustzone: set CPU frequency in tee environment
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-09-10 23:10:06 +08:00
liaoao
d63e3962bf qemu:fdt:add device tree support for goldfish arm/arm64
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-09-10 23:10:06 +08:00
wangming9
c8a4bdf21a arch/arm: GoldFish Platform support
Summary:
    Adding virtual evaluate platform GoldFish. Which is based on
    Android Goldfish Emulator, it's a ARM virt board but Android
    enhance it with more featue.
    The patch set goldfish as a arm chip.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-09-10 23:10:06 +08:00
liaoao
78c942a05a devicetree: add devicetree support for arm/arm64
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-09-10 14:28:41 +03:00
hujun5
90fba56d2e timer/trustzone: set CPU frequency in tee environment
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-09-10 14:28:41 +03:00
hujun5
d9cbf84d86 arm/oneshot: rm sched_[un]lock
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-09-09 20:26:32 +08:00
hujun5
3f8f3340d1 pic32mx: sched_lock should replace with enter_critical_secion
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-09-09 10:26:03 +08:00
hujun5
0b23a316ca sam_hsmci: rm sched_[un]lock
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-09-09 00:21:29 +08:00
shipei
f150699d7a audio:add media session support for sim_alsa audio_ops_s interface
fix Compiler Warning:initialization of ‘int (*)(struct audio_lowerhalf_s *, void *)’
from incompatible pointer type ‘int (*)(struct audio_lowerhalf_s *)’ [-Wincompatible-pointer-types]

Signed-off-by: shipei <shipei@xiaomi.com>
2023-09-09 00:13:06 +08:00
Jukka Laitinen
a6388b8843 arch/risc-v/src/mpfs: Add ksz9477 initialization
This adds initialization of the ksz9477 switch when used instead of
a PHY, directly connected to SGMII

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-09-08 22:34:27 +08:00
Michal Lenc
6d0151c8da sam_usbdevhs.c: fix compile warning
chip/sam_usbdevhs.c:2474:11: warning: 'response' may be used uninitialized [-Wmaybe-uninitialized]
 2474 |           sam_ctrlep_write(ep0, response.b, nbytes);
      |           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
chip/sam_usbdevhs.c:1845:13: note: by argument 2 of type 'const uint8_t *' {aka 'const unsigned char *'} to 'sam_ctrlep_write' declared here
 1845 | static void sam_ctrlep_write(struct sam_ep_s *privep, const uint8_t *buffer,
      |             ^~~~~~~~~~~~~~~~
chip/sam_usbdevhs.c:2001:24: note: 'response' declared here
 2001 |   union wb_u           response;
      |                        ^~~~~~~~

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-09-08 15:56:52 +03:00
Petro Karashchenko
f39de6fd1a arch/arm/armv[7|8]-m: implement dcache clean as barrier in write-through mode
This change fixes the issue when SAMv7 GMAC sometimes does not start packet
transmission. The issue is that EMAC_NCR_TSTART is written to EMAC_NCR register
while tx descriptor is not delivered to memory.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-08 11:54:04 +08:00
Eren Terzioglu
a26996fb3b xtensa/esp32s3: Add support to TWAI/CANBus controller 2023-09-08 01:49:43 +08:00
hujun5
83ba72e4b4 cxd56xx: rm sched_[un]lock
According to the current implementation, "cxd56_cpu1siguninit" will only
be called once during the NuttX startup phase,
and it won't involve scenarios of multi-threaded concurrent access.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-09-08 01:47:40 +08:00
Michal Lenc
c2bc3dfb12 samv7: add support for SD card detection from CD/DAT3 line
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).

This commit adds CD/DAT3 line card detection support for SAMv7 MCU.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-09-08 01:13:36 +08:00
yanxiaowei
5c780f6697 sim/framebuffer: fix memory leak
LeakSanitizer: detected memory leaks in XStringListToTextProperty

Signed-off-by: yanxiaowei <yanxiaowei@xiaomi.com>
2023-09-07 11:21:58 +03:00
cuiziwei
ba73272f67 nuttx/sim:add up_irq_enbale function.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2023-09-06 21:42:42 +03:00
Jukka Laitinen
b750f94896 arch/risc-v/src/mpfs: Generate an unique locally administrated MAC address
Add a function to read PolarFire's serial number from system controller, and use the first five digits as device's mac address

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-09-07 00:53:00 +08:00
Jari Nippula
ef18d2b599 arch/riscv/src/mpfs/mpfs_ethernet.c: discard err rxframe in int work
Workaround to avoid deadlock situation: The RX shall not try to wait for complete
frame in case there is RX errors detected.

In case mpfs_receive is called, it keeps waiting for complete frame and
also keeps the net_lock locked. In the mean while, the TX may run out of free
descriptors, but can not get net_lock mutex lock to be able to release used
descriptors. If there are no free TX descs it disables RX interrupts because
it may require to send response to the received frame.
So, TX side keeps RX interrupts disabled due to lack of free descriptors and
RX blocks TX to release those descs by stubbornly waiting for complete frame.
2023-09-07 00:53:00 +08:00
Xu Xingliang
a2df576ecf kasan: add option to disable read/write checks
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2023-09-07 00:41:43 +08:00
yintao
cb105192c7 nuttx/sim: Sim_rptun support configuring whether the master will automatically boot slave
Signed-off-by: yintao <yintao@xiaomi.com>
2023-09-06 17:05:55 +03:00
Eero Nurkkala
0152b031a4 risc-v/mpfs: enhance rpmsg throughput
RPMSG is associated with the use of HPWORK / LPWORK queues.
After sending a message to the remote end (Linux), the system
waits for an ack before proceeding. Unfortunately this may
take sometimes more time than one would expect. Ack waiting is
also unnecessary: nothing is done with that information. Even
worse, the net_lock() is also held during the blocked time so
it blocks other network stacks that are unrelated to this.

Also reorganize the mpfs_opensbi_*.S so that the trap
handler is easily relocated in the linker .ld file without
the need to relocate the utils.S. This makes it easier to
separate the files into own segments. The trap file should be
located in the zero device.

Moreover, provide support for simultaneous ACK and message
present handling capabilities in both directions. There are
times when both bits are set but only other is being handled.

In the end, the maximum throughput of the RPMSG bus increases
easily 10-20% or even more.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-09-06 14:32:11 +08:00
Seppo Hirvela
67ad63c7a4 risc-v/mpfs: ihc: fix to work with the latest NuttX OpenAMP version 2023-09-06 14:32:11 +08:00
Jani Paalijarvi
a1aebb7a64 risc-v/mpfs: ihc: Minor fixes
Remove unnecessary VQID shifting (16 -> 0).
Give an error if RPTUN init fails.
2023-09-06 14:32:11 +08:00
Jani Paalijarvi
cc5e8222b3 risc-v/mpfs: ihc: Increase RPMSG buffer size
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2023-09-06 14:32:11 +08:00
Jani Paalijarvi
3bd4bd6196 risc-v/mpfs: ihc: Make Vring addresses configurable 2023-09-06 14:32:11 +08:00
Jani Paalijarvi
00cb72bc09 risc-v/mpfs: ihc: Make IHC HSS workaround configurable 2023-09-06 14:32:11 +08:00
Philippe Leduc
87cec56154 Handle GPIO IRQs
Add board buttons
2023-09-06 12:30:35 +08:00
Philippe Leduc
5b7c948aef Add GPIO
Add userleds
2023-09-06 12:30:35 +08:00
Petro Karashchenko
12ea47b10f arch/xtensa/esp32s3: add UART2 support
This commits adds support of UART2 for EPS32S3 and fixes pin mode
assignment for iomux mode

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-06 02:40:49 +08:00
Stuart Ianna
99d630b18d arch/risc-v/litex/litex_sdio: Address race condition in eventwait.
Wraps litex_eventwait in a critical section to handle the case that an event can occur before it's waited on.
2023-09-06 02:23:57 +08:00
Tiago Medicci Serrano
8a51534903 esp32s3/i2s: Check compatibility of the current master clock set
The master clock frequency should be multiple of the sample rate
and bit clock at the same time. Then, check if the current master
clock satisfies such a condition and set it accordingly otherwise.
2023-09-05 13:33:05 +08:00
Tiago Medicci Serrano
f1b459347b esp32s3/i2s: Add interface to stop the I2S streams
In order to gracefully stop the I2S stream, add an interface to set
a `streaming` status variable that sets the `AUDIO_APB_FINAL` flag
that will be handled by the upper layers of the audio subsystem.
2023-09-05 13:33:05 +08:00
Alan Carvalho de Assis
5065849ab6 esp32s3/i2s: Add initial support to I2S peripheral
The I2S peripherals are now supported for both receiving and
transmitting controllers.
2023-09-05 13:33:05 +08:00
Tiago Medicci Serrano
45d17551b3 esp32s3/dma: Set the DMA descriptor according to RX or TX operation
According to RX/TX operation, the DMA descriptors (inlink/outlink)
should be set differently. When setting the inlink, the `suc_eof`
field must be cleared by software (it will be set by hardware when
a packet is received). Similarly, the `length` field will be set
by hardware a packet is received.
2023-09-05 13:33:05 +08:00
Tiago Medicci Serrano
e7eeb99139 esp32s3/dma: Define macros on header files to be used by the system
Define macros used to access the registers of the GDMA channels
according to the selected channel in the header file, enabling them
to be used by other drivers.
2023-09-05 13:33:05 +08:00
Tiago Medicci Serrano
a513770fcb esp32s3/dma: Split the setup and load of the DMA descriptors
By splitting into two different functions the setup of the DMA
descriptors and the action of loading it to the GDMA outlink
register, it enables us to "cache" DMA descriptors ready to be send
and, then, just load them whenever we are able to actually send it.
2023-09-05 13:33:05 +08:00
Tiago Medicci Serrano
d26212bd39 esp32s3/dma: Fix loading the DMA descriptor address
The macro `SET_BITS` only sets the bits according to the bit mask
and, once it's being used to set the address field of the GDMA
inlink/outlink register, it's necessary to clean all the bits
corresponding to that field that were eventually setup previously
to avoid messing with the bits that correspond to the current
address being setup.
2023-09-05 13:33:05 +08:00
Jakub Zdroik
96a2196beb fix argument of nxsem_wait_uninterruptible 2023-09-04 23:20:32 +08:00
wangjianyu3
8a13da322d binfmt: Support arch copy section by self for dynamic code loading
This option enables architecture-specific memory copy for dynamic code loading.

For example, Ambiq has MRAM regions for instruction which can't load by
the memcpy directly.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
2023-09-04 12:23:26 +08:00
Eero Nurkkala
f5cdfa73dc risc-v/mpfs: clear L2 before use
SiFive document: "ECC Error Handling Guide" states:

"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."

Clean the cache at this early stage so no ECC errors will be flooding later.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-09-01 19:28:54 +08:00
simbit18
a642b7a54f Fix Kconfig style
Remove extra TABs
Add comments
2023-08-31 18:08:22 +03:00
Philippe Leduc
98e998b934 Add i2c support for the i.MX8MP
Enable INA219 on the Verdin board
2023-08-31 10:35:46 -03:00
Ville Juven
779741d1d9 riscv/riscv_pmp.c: Improve NAPOT area validity checks
Check that the base address and region size are properly aligned with
relation to each other.

With NAPOT encoding the area base and size are not arbitrary, as when
the size increases the amount of bits available for encoding the base
address decreases.
2023-08-30 19:04:22 +03:00
Jukka Laitinen
697472dc07 arch/risc-v/src/mpfs/mpfs_ddr.c: Re-write write calibration
Clean up the code and remove un-used global variables & structs

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-30 12:28:21 +03:00
Jukka Laitinen
f10dab5531 arch/risc-v/src/mpfs: Sync some of the libero config macros with HSS reference code
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-08-30 12:28:21 +03:00
Jukka Laitinen
c80b8fdf24 arch/risc-v/src/mpfs/mpfs_ddr.c: Add a simple prng for memory training code
Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran

This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-30 12:28:21 +03:00
Jukka Laitinen
f9b5918462 arch/risc-v/src/mpfs/mpfs_ddr.c: Make sure that DDRC is in reset when starting the training
Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-30 12:28:21 +03:00
Jukka Laitinen
6baeb7217e arch/risc-v/src/mpfs/mpfs_ddr.c: Correct memory test timeouts
Especially the write calibration must bail out if the memory test timeouts,
otherwise the device will get stuck in running the memory test in sequence,
and it will always timeout.

Negative error value was also not properly returned from mpfs_mtc_test.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-30 12:28:21 +03:00
Jukka Laitinen
d38eebc0e9 arch/risc-v/src/mpfs/mpfs_ddr.c: Don't auto-determine the write latency
It doesn't make sense to try to auto-determine write latency, it may pass with too low value.

Keep the existing implementation if the write latency has been set to minimum
value, otherwise just set it.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-30 12:28:21 +03:00
Jukka Laitinen
8fb2e41994 arch/risc-v/src/mpfs/mpfs_ddr.c: Correct the DDR training dq/dqs status check
It was checking a wrong register for dq/dqs window size.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-30 12:28:21 +03:00
chao an
664927c86e mm/alloc: remove all unnecessary cast for alloc
Fix the minor style issue and remove unnecessary cast

Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-30 14:34:20 +08:00
chao an
b60f01a55b inode/i_private: remove all unnecessary cast for i_private
Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-29 08:58:07 +02:00
chao an
7aa45305b7 fs/inode: remove all unnecessary check for filep/inode
Since VFS layer already contains sanity checks, so remove unnecessary lower half checks

Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-29 09:47:11 +08:00
Michal Lenc
03e5c0217b samv7: allow usage of QSPI in SPI mode for all MCUs
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-08-28 17:39:51 +03:00
chao an
518dcbdaad sim/internal: add typedef pid_t to enhance sim compatibility
enhance sim compatibility on windows

Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-28 17:12:45 +03:00
Ville Juven
01cc1687b3 mpfs/mpfs_i2c.c: Replace 1 second timeout with Time-on-Air based timeout
Calculate how long an I2C transation will take in microseconds, and use
this as the timeout for mpfs_i2c_sem_waitdone.

The reason for doing this is not to keep an i2c bus reserved for the full
1 second timeout, if e.g. a sensor is not on the bus / is faulty and
non-responsive. Reading the other sensors will be blocked for a relatively
long time (1 second) in this case. This fixes such behavior.
2023-08-28 21:16:23 +08:00
Xiang Xiao
47faeeb360 tls: Move task_tls_alloc and task_tls_destruct to libc
so task_tls_destruct can be called from usrspace, which is required by:
https://github.com/apache/nuttx/pull/10288

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-28 11:02:18 +03:00
raiden00pl
2fffd7dad6 arch/stm32h7: add RPTUN support 2023-08-26 03:35:32 +08:00
raiden00pl
a6c25f657d arch/stm32h7: add CM4 core support 2023-08-26 03:35:32 +08:00
raiden00pl
86134461f3 arch/stm32h7: use STM32_CPUCLK_FREQUENCY to initialize perf 2023-08-26 03:35:32 +08:00
raiden00pl
4c358419f0 arch/stm32h7: add an option to bypass clock configuration 2023-08-26 03:35:32 +08:00
raiden00pl
5ddded5561 arch/stm32h7/rcc: default value for BOARD_FLASH_PROGDELAY 2023-08-26 03:35:32 +08:00
raiden00pl
4c9d405a97 arch/stm32h7: add HSEM support 2023-08-26 03:35:32 +08:00
Xiang Xiao
a967da5270 arch/riscv: Move -mcmodel=medany from Make.defs to Toolchain.defs
to avoid the code duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-25 21:22:47 +03:00
chao an
563125fde3 make/archive: Use the full path name when matching or storing names in the archive
This pr will avoid targets with the same name can not be archive in the same library

Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-26 01:21:10 +08:00
SPRESENSE
6d44c42707 arch/arm/src/cxd56xx: Fix file path on top comment
Fix file path described in top comment for each files.
2023-08-26 01:20:32 +08:00
SPRESENSE
f7400a857d drivers/audio/cxd56: Move cxd56 sources into arch/cxd56xx
CXD56 audio functions are inside of the CXD56.
So implementation of it should be under arch directory.
2023-08-26 01:20:32 +08:00
chengkai
d867c46bbc serial/uart/h5: add bt h5 uart serial driver
Signed-off-by: chengkai <chengkai@xiaomi.com>
2023-08-25 17:17:37 +08:00
Stuart Ianna
50f0fd4df2 risc-v/litex: Add system reset and access to core control registers. 2023-08-25 17:16:28 +08:00
Roy Feng
937312242e esp32: Fix build warning
And an incorrect log output
2023-08-25 17:06:32 +08:00
Michal Lenc
606b6d9310 samv7: add support for PWM polarity settings
This commit adds function pwm_set_polarity() that setups channel
polarity based on input info from application layer.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-08-24 18:25:47 -03:00
Philippe Leduc
e084c52e12 Add i.MX8MP Cortex-M7 port for NuttX 2023-08-24 20:10:48 +08:00
raiden00pl
c3f8753ecd Documentation: migrate STM32L4 2023-08-24 17:56:39 +08:00
Anner J. Bonilla
24e45d071e Pinephone Pro port just nsh
Pinephone Pro port just nsh

Status:
booting till GICD / IRQ issue

style cleanups

start to fix style checks

revert offset

whitespaces

revert a64 bringup file

prob last cleanup

more cleanups

remove dts

move changes from a64 hardware specific folders to rk3399

undo common changes (except head.s)

revert gitignore

missing irq.h and rk3399_serial.c need to finish cleaning them up

WIP

add source for load address

make debug print hex again add board include

Pinephone Pro port just nsh

Status:
booting till GICD / IRQ issue

style cleanups

start to fix style checks

revert offset

whitespaces

revert a64 bringup file

prob last cleanup

more cleanups

remove dts

move changes from a64 hardware specific folders to rk3399

undo common changes (except head.s)

revert gitignore

missing irq.h and rk3399_serial.c need to finish cleaning them up

WIP

add source for load address

remove ccache, add board memory map

remove board reset
2023-08-24 11:16:31 +08:00
chao an
ba2601deb6 Toolchain: strict GCC version check from GCC-12.2 to GCC-12
Toolchain related detection errors are still not resolved on GCC-12.3

Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-23 23:52:17 +08:00
Tia
fc8848ec18 Fix bugs related to software flow control in file stm32_hciuart.c. 2023-08-23 23:23:42 +08:00
raiden00pl
7b82a1ac9c armv7-m/mpu.h: add macro to configure shared memory region 2023-08-22 23:34:57 +08:00
raiden00pl
3da199c71d armv8-m/mpu.h: add macro to configure shared memory region 2023-08-22 23:34:57 +08:00
Ville Juven
8071a55198 riscv/riscv_addrenv.c: Allocate heap for default task stacksize
1 page might not be enough, if the task has a bigger stack. Best effort
is to allocate the default amount, however this won't work will all
tasks either.
2023-08-22 23:21:09 +08:00
Eero Nurkkala
5bd0140d9f risc-v/mpfs: mpfs_usb: fix tx fifo size setup
Currently TX_FIFO_SIZE is not altered in mpfs_ep_set_fifo_size(),
but all paths (RX and TX) change MPFS_USB_RX_FIFO_SIZE only.
Fix the TX_FIFO_SIZE setup.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-08-22 20:26:45 +08:00
cuiziwei
1a8027d625 nuttx/arch:add -Wno-psabi to Toolchain.defs
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2023-08-22 01:33:30 +08:00
raiden00pl
d31402bf3c arch/{stm32|stm32f7}/stm32_mpuinit.h: cosmetics 2023-08-21 19:22:52 +08:00
liqinhui
0d39246b4e sim/posix: Add the host_system interface used to execute the host command
Encapsulate the host system/popen interface to host_system.

Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2023-08-21 17:40:40 +08:00
raiden00pl
78c88b5e78 arch/nrf53: FLASH cache only for netcore, disable by default as it breaks rptun
After sevaral resets of the chip after programming, rptun stops working correctly.
Simple test with RPMSG UART causes a lock:

  on the netcore:
    nsh>cat /dev/ttyproxy

  on the appcore:
    nsh>echo xxx > /dev/ttyproxy

The problem doesn't occur with NRF53_FLASH_PREFETCH=n
2023-08-21 17:34:36 +08:00
raiden00pl
187a067866 arch/nrf53/rptun: remove dependency on DEV_SIMPLE_ADDRENV 2023-08-21 17:34:36 +08:00
raiden00pl
45a542cb14 arch/nrf53: move SPU configuration to a separate file 2023-08-21 17:34:36 +08:00
raiden00pl
8ebc0dc9e8 cmake: port 99b0bad94e arch/armv8-m: DSP extension is optional 2023-08-21 17:34:36 +08:00
liaoao
9231dbe716 cpuinfo:armv6: select ARCH_HAVE_CPUINFO by default
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-21 17:33:50 +08:00
qinwei1
630b5f32a2 arm64: IMX8 MEK board support
Summary

   Support for imx8qm MEK evaluate board

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 14:23:05 +08:00
qinwei1
30354e5767 arm64: IMX8 platform (Cortex-A53) support
Summary

   Support for imx8 platform, this is a very initialize version

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 14:23:05 +08:00
yintao
4b5910efc1 nuttx/sim: simlulator rptun powerdown
Signed-off-by: yintao <yintao@xiaomi.com>
2023-08-21 13:21:50 +08:00
qinwei1
5b7267bf66 arm64: remove unnecessary trace interface
Summary
    this is a old implement for Arm64 trace but will failed
compile when enable CONFIG_SCHED_INSTRUMENTATION_SWITCH
    remove it since it will never use for trace framework

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-21 09:49:02 +08:00
hanqiyuan
1a832eb554 xtensa: enable -Oz for xtensa to reduce codesize 2023-08-21 02:58:25 +08:00
hujun5
f1b6cf78da arch/arm: add CONFIG_ARCH_TRUSTZONE_SECURE to some code
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
hujun5
a96c6f1abf arch/arm: Add the secure handling to gic
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
Xiang Xiao
7bb563dfe9 arch/arm: Remove CONFIG_ARCH_TRUSTZONE_BOTH related stuff
represent tee by CONFIG_ARCH_TRUSTZONE_SECURE instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-21 00:06:25 +08:00
raiden00pl
e8be4d0000 arch/nrf91: remove empty nrf91_modem_sock.h 2023-08-20 22:53:38 +08:00
raiden00pl
b927cf68c6 arch/nrf91: add missing include guards 2023-08-20 22:53:38 +08:00
huangkai8
8f297f79d8 Avoid hard fault when reading vectors in text section. 2023-08-20 14:35:05 +03:00
Xiang Xiao
7f32eaa13e arm/qemu: Remove qemu_net.c which isn't needed anymore
after the follow patch:
commit 9aa57b6c53
Author: wangbowen6 <wangbowen6@xiaomi.com>
Date:   Wed Mar 22 11:49:43 2023 +0800

    virtio: add virtio framework in NuttX

    1. virtio devics/drivers match and probe/remote mechanism;
    2. virtio mmio transport layer based on OpenAmp (Compatible with both
       virtio mmio version 1 and 2);
    3. virtio-serial driver based on new virtio framework;
    4. virtio-rng driver based on new virtio framework;
    5. virtio-net driver based on new virtio framework
       (IOB Offload implementation);
    6. virtio-blk driver based on new virtio framework;
    7. Remove the old virtio mmio framework, the old framework only
       support mmio transport layer, and the new framwork support
       more transport layer and this commit has implemented all the
       old virtio drivers;
    8. Refresh the the qemu-arm64 and qemu-riscv virtio related
       configs, and update its README.txt;

    New virtio-net driver has better performance
    Compared with previous virtio-mmio-net:
    |                        | master/-c | master/-s | this/-c | this/-s |
    | :--------------------: | :-------: | :-------: | :-----: | :-----: |
    | qemu-armv8a:netnsh     |  539Mbps  |  524Mbps  | 906Mbps | 715Mbps |
    | qemu-armv8a:netnsh_smp |  401Mbps  |  437Mbps  | 583Mbps | 505Mbps |
    | rv-virt:netnsh         |  487Mbps  |  512Mbps  | 760Mbps | 634Mbps |
    | rv-virt:netnsh_smp     |  387Mbps  |  455Mbps  | 447Mbps | 502Mbps |
    | rv-virt:netnsh64       |  602Mbps  |  595Mbps  | 881Mbps | 769Mbps |
    | rv-virt:netnsh64_smp   |  414Mbps  |  515Mbps  | 491Mbps | 525Mbps |
    | rv-virt:knetnsh64      |  515Mbps  |  457Mbps  | 606Mbps | 540Mbps |
    | rv-virt:knetnsh64_smp  |  308Mbps  |  389Mbps  | 415Mbps | 474Mbps |
    Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
          Tested in QEMU 7.2.2

    Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
    Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-20 14:33:17 +03:00
Petro Karashchenko
075738cf14 net/ip: print ip addresses using ip4_addrN macro
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-08-19 13:28:21 -03:00
Tiago Medicci Serrano
382debc996 esp32_c3_s3/wifi_ble: Use nxsem_trywait to take semphr from ISR
Use the non-blocking `nxsem_trywait` to try to take the semaphore
during the interrupt handler.
2023-08-19 18:40:31 +08:00
chenrun1
709301cbfd hostfs:support SEEK_CUR
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
2023-08-19 01:48:48 +08:00
liaoao
c31e869fac cpuinfo: show cpufreq when hardware perfermance counting enabled
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-19 01:40:10 +08:00
Jukka Laitinen
f5575479f3 arch/risc-v/src/mpfs: Clean up BCLKSCLK training
This adds a config flag to remove manual bclksclk training if one wants
to just use the controller's own training.

Manual addcmd training depends on the manual bclksclk training, so this
also adds this dependency in Kconfig.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-19 01:27:56 +08:00
Jukka Laitinen
bcfa6a8c5d arch/risc-v/src/mpfs/mpfs_ddr.c: Remove unused fields in mpfs_ddr_priv_s
There are leftover unused parameters in mpfs_ddr_priv_s. Just remove them.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-19 01:27:56 +08:00
Jukka Laitinen
340ae8c753 arch/risc-v/src/mpfs/mpfs_ddr.c: Simplify code performing write calibration
This keeps the same functionality, the original code is just overly complicated

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-19 01:27:56 +08:00
simbit18
70ab01a20b Fix Kconfig style
Replace help => ---help---
Remove spaces from Kconfig
Add comments
2023-08-18 16:36:04 +03:00
Lucas Saavedra Vaz
e02b203311 arch/xtensa/esp32s3: Update MCUboot build process
Change the MCUboot build process to, in the future, deprecate the esp-nuttx-bootloaders repository.
2023-08-18 14:44:11 +08:00
Lucas Saavedra Vaz
4bcc930535 arch/xtensa/esp32s2: Update MCUboot build process
Change the MCUboot build process to, in the future, deprecate the esp-nuttx-bootloaders repository.
2023-08-18 14:44:11 +08:00
Lucas Saavedra Vaz
60fdc9cb72 arch/xtensa/esp32: Update MCUboot build process
Change the MCUboot build process to, in the future, deprecate the esp-nuttx-bootloaders repository.
2023-08-18 14:44:11 +08:00
yanghuatao
aa34885c8b arch/arm: Fix arm_backtrace_unwind.c -Wmaybe-uninitialized and -Wint-conversion warning on n606
(1)common/arm_backtrace_unwind.c:528:18: warning: 'ctrl.lr_addr' may be used uninitialized in this function [-Wmaybe-uninitialized]
(2)common/arm_backtrace_unwind.c:626:27: warning: assignment to 'long unsigned int' from 'uint8_t (*)[]' {aka 'unsigned char (*)[]'} makes integer from pointer without a cast [-Wint-conversion]

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2023-08-18 12:20:21 +08:00
Jukka Laitinen
6a5d00f68c arch/risc-v/src/mpfs: Add CFG_DDR_SGMII_PHY_RPC156 register setting for DDR training
Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-17 17:50:37 +08:00
Jukka Laitinen
cd9ac3cf70 arch/risc-v/src/mpfs/mpfs_ddr.c: Don't continue training process if "verify" step fails
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-08-17 17:50:37 +08:00
Stuart Ianna
34bfa2f7ba arch/risc-v/litex: Add platform specific tickless implementation.
Adds a platform specific implementation for tickless schedular operation. This includes:
 - Tickless operation for vexriscv cores.
 - Tickless operation for vexriscv-smp cores.
 - Ticked operation for vexriscv-smp cores.

Ticked operation for vexriscv core has been refactored.

Additional default configuration added to demonstrate operation.

Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.
2023-08-16 16:59:27 +08:00
Ryan MacDonald
074cf51268 Fix: s32k1 s32k3 kinetis: add propseg to ctrl1 timing mask 2023-08-16 10:09:40 +03:00
Tiago Medicci Serrano
5adb9de00b espressif: Update esp-hal-3rdparty version
The newest version of the esp-hal-3rdparty includes general
bugfixes and includes components necessary to build the IDFboot.
2023-08-15 13:39:22 -03:00
wangming9
e953715e6d arch/arm: add qemu support for ARM32
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-15 23:56:41 +08:00
yinshengkai
88f3bc77f1 toolchain: detect use of large stack variables
partition/fs_gpt.c:384:5: warning: stack usage might be 288 bytes [-Wstack-usage=]
  384 | int parse_gpt_partition(FAR struct partition_state_s *state,

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-08-15 14:50:27 +03:00
Tiago Medicci Serrano
281ab83309 esp32s3: Use PANIC() instead of assert(0)
Considering kernel code, it's reasonable to use `PANIC()` instead
of `assert(0)` to handle with situations that require abort. Unlike
`assert`, `PANIC()` doesn't dependent on `NDEBUG`.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
01b6c87b15 esp32s3: Implement the Wi-Fi/BLE coexistence
ESP32-S3 has only one 2.4 GHz ISM band RF module, which is shared
by Bluetooth and Wi-Fi, so Bluetooth can’t receive or transmit data
while Wi-Fi is receiving or transmitting data and vice versa.
Under such circumstances, ESP32-S3 uses the time-division
multiplexing method to receive and transmit packets.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
7d605551cd esp32s3/wifi: Enable peripheral interrupt to the same CPU interrupt
The low-level Wi-Fi driver registers two peripheral interrupts to
the same CPU interrupt. Although the registered ISR is the same for
both peripherals interrupt, it's needed to call `up_enable_irq` to
ensure that the interrupt matrix is being set accordingly.

Please note that the current implementation of the  ESP32-S3's IRQ
driver - although allow us to set a callback for each IRQ, which
represents the peripherals interrupt - doesn't allow us to call
both callbacks when these IRQs refers to a same CPU interrupt.
`g_cpu0_intmap` (or `g_cpu1_intmap`) associates each CPU interrupt
to a single IRQ/peripheral and, then, when a CPU interrupt is
triggered, only the last registered IRQ's callback will be called.
This isn't a problem here because 1) the registered callback is the
same for both IRQ's (in fact, it considers the CPU interrupt) and
2) we know in advance which peripheral interrupts will be attached
to which CPU interrupt and, then, we can set them directly.
2023-08-14 16:29:21 -03:00
Petro Karashchenko
655d00b1e7 arch/xtensa/esp32s3: initial effort to get BLE running on ESP32-S3
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
33f03fc98c esp32s3/wlan: Always run wlan_rxpoll work queue
Even if we were unable to get a free IOB, trigger the work queue
to make sure that no old packet is waiting to be handled by the
network upper layers.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
012dddf7c9 esp32s3/wlan: check for all connections on wlan_txpoll
This prevents us from getting stuck while polling the different
network structures in `devif_poll_connections`. This is useful for
Wi-Fi/Bluetooth coexistence, specifically.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
6589887284 esp32s3/wlan: check if the network device's IOB isn't null
Before adding the upper layer network device's IOB to the TX queue
of the wireless driver, check if it isn't null.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
ec4149c61d esp32s3/hardware: Update regi2c_ctrl.h functions name 2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
6089f58f00 esp32s3/irq: Enhance IRQ subsystem
- Fix macro values from `arch/xtensa/include/esp32s3/irq.h`
- Remove references to unexisting edge-triggered CPU interrupts
- Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
31476bcb34 esp32s3/rtc: Initialize RTC subsystem
RTC subsystem controls not only the RTC itself but functions that
use RTC-enabled features like Bluetooth and Wi-Fi. Initialization
must be performed during the system start-up.
2023-08-14 16:29:21 -03:00
Tiago Medicci Serrano
7dafbb05a1 esp32s3/peripherals: Add initialization routine for the peripherals
It provides an initialization function that performs the
peripherals' initialization routine during the chip startup.
2023-08-14 16:29:21 -03:00
Xiang Xiao
14563aa48c arch/armv7r: Sync gic/timer with armv7-a and armv8-a
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-14 14:51:01 -03:00
Xiang Xiao
e4dea90725 arch/armv7-a: Update the macro definition in gic.h
https://developer.arm.com/documentation/ihi0048/b

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-14 14:51:01 -03:00
raiden00pl
89174e6a1a arch/stm32h7: use correct name for bit 2 in STM32_PWR_CR3 register 2023-08-14 23:42:37 +08:00
David Sidrane
60840f1ed2 imxrt:Serial Preserve all but W1C bit in SR
SR contains configuration bits that need to be preserved.
2023-08-14 18:23:59 +03:00
raiden00pl
b73e1b9591 arch/{nrf52|nrf53|nrf91}: handle I2C errors in interrupt mode 2023-08-14 17:51:48 +08:00
raiden00pl
5572552024 arch/nrf53: port 6e8f25ba3b change from nrf52
Added config setting for NRF53 I2C timing bug workaround
2023-08-13 11:45:06 -03:00
raiden00pl
eec59015f0 arch/{nrf53|nrf91}: port cc99d94cfd change from nrf52
Fixed NRF52 I2C register naming
2023-08-13 11:45:06 -03:00
raiden00pl
3a61db4c7b arch/nrf53: port d7aea88727 change from nrf52
Changed NRF53 USB initialization to check for power via USBREGSTATUS instead of waiting for interrupt
2023-08-13 11:45:06 -03:00
raiden00pl
fc4ddfb1f4 arch/nrf52/nrf52_twi.h: fix condition
missing prefix CONFIG_* in commit 6e8f25ba3b
2023-08-13 11:45:06 -03:00
raiden00pl
bcef7d32f5 arch/nrf52/nrf52_i2c.c: remove unnecessary include introduced in cc99d94cfd 2023-08-13 11:45:06 -03:00
simbit18
693b034827 arch/arm/src/nrf91/Kconfig: Fix Kconfig style
Add TABs
Add comments
Remove spaces from Kconfig file
2023-08-13 11:44:19 -03:00
Xiang Xiao
bd30d1a4d5 arch: Move trustzone related setting to common place
to share the security setting between arm32 and arm64

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-13 08:43:01 +02:00
Xiang Xiao
b183114d43 arch/arm: Change the default value to ARCH_TRUSTZONE_NONSECURE
since nuttx normally run inside the non secure execution environment

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-08-13 08:43:01 +02:00
Brian Doherty
d7aea88727 Changed NRF52 USB initialization to check for power via USBREGSTATUS instead of waiting for interrupt, in case we've been launched from a bootloader. 2023-08-13 06:47:14 +08:00
Brian Doherty
cc99d94cfd Fixed NRF52 I2C register naming. 2023-08-13 06:46:57 +08:00
Brian Doherty
6e8f25ba3b Added config setting for NRF52 I2C timing bug workaround. 2023-08-13 06:46:31 +08:00
wangming9
c928acc9ff perf: The new configuration supports hardware performance counting
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting,solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.

This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion

To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-12 02:20:44 +08:00
TimJTi
d0613fa165 SAMA5D2 MCAN Error corrections plus changes to improve clarity
Kconfig typo
2023-08-12 02:20:09 +08:00
David Sidrane
2dc6365e24 s32k3xx:lpi2c fix status handeling & race
s32k3:lpi2c:Simplify DMA and Non DMA usage

s32k3xx: lpi2c dma invalidate cache after exchange

s32k3xx:lpi2c fix timeout not stopping dma
2023-08-11 13:41:49 -03:00
David Sidrane
afdce6e8c2 imxrt:lpi2c fix status handeling & race
imxrt:lpi2c:Simplify DMA and Non DMA usage

imxrt: lpi2c dma invalidate cache after exchange

imxrt:lpi2c fix timeout not stopping dma
2023-08-11 13:41:49 -03:00
David Sidrane
eb06843178 s32k1xx:lpi2c fix status handeling & race
s32k1:lpi2c:Simplify DMA and Non DMA usage

s32k1xx: lpi2c dma invalidate cache after exchange

s32k1xx:lpi2c fix timeout not stopping dma
2023-08-11 13:41:49 -03:00
Peter van der Perk
755e3beba9 s32k3xx: lpspi dma invalidate cache after exchange 2023-08-11 13:41:49 -03:00
Peter van der Perk
87a51f4faa imxrt: lpspi dma invalidate cache after exchange 2023-08-11 13:41:49 -03:00
Alexander Lunev
cfbee60932 arm/stm32h7: stm32h7x5: fixed typo on SPI header inclusion 2023-08-11 22:39:38 +08:00
chao an
fc354a1446 arm/clang: enhance compatibility of clang compiler
The naming of the clang configuration file has changed after version 14
This commit will enable the compatibility with clang-14/15/16/17

Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-11 20:17:36 +08:00
chenxiaoyi
fd34be15eb sim: use correct size to avoid buffer overflow
Fix buffer overflow issue from PR #10128, since the sizeof
xcpt_reg_t is different on 32/64 bit platform.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2023-08-11 20:13:28 +08:00
liaoao
dffab1e0c6 qemu: add devicetree support for arm64
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-11 00:46:50 +08:00
chenxiaoyi
6d6e1aea3b sim: Fix sim stack smashing problem
The reason is that the new created task receives signal while
it has not entered its stack frame.

Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
2023-08-10 23:30:22 +08:00
ligd
324aa7d17f sim: rptun support panic & reset
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-10 23:13:40 +08:00
qinwei1
37e69cdeb0 arch/arm64: enable for arm64 virt to choice CPU core
Summary
    Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
    the change do this

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 20:48:19 +08:00
hujun5
b82ccd6621 arch/timer: frequency 0 should not be set
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-08-10 17:59:21 +08:00
qinwei1
d8e1022b6f arm64: add hostfs support
Sumary
   add hostfs support for arm64, it's a copy
from arm32.

Note:
   it's not support for opendir and readdir, command
like ls will not work.

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-08-10 17:58:34 +08:00
wangbowen6
cbb594dcbc sim: add set/get_power for sim_framebuffer.c
add set/get_power operation for sim_framebuffer to avoid assert
in fb_ioctl(cmd= FBIOSET_POWER/FBIOGET_POWER)

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2023-08-10 15:57:57 +08:00
wangbowen6
8db4abd5dd arm_backtrace_sp: check the addr after every operation to addr
Should check the addr every time it changed to avoid crash in
backtrace.

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2023-08-10 15:52:23 +08:00
liaoao
c1eecd7c4f procfs:add armv6-m cpuinfo
signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-10 14:13:35 +08:00
wangming9
f4e33e488d arch/arm64: Fixed arm64 backtrace support for other processes
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-10 13:35:59 +08:00
zhangyuan21
b5f266d5af armv8-m: the FPSCR[18:16] LTPSIZE field in exception_common
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-10 13:11:45 +08:00
wangbowen6
9aa57b6c53 virtio: add virtio framework in NuttX
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
   virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
   (IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
   support mmio transport layer, and the new framwork support
   more transport layer and this commit has implemented all the
   old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
   configs, and update its README.txt;

New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
|                        | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh     |  539Mbps  |  524Mbps  | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp |  401Mbps  |  437Mbps  | 583Mbps | 505Mbps |
| rv-virt:netnsh         |  487Mbps  |  512Mbps  | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp     |  387Mbps  |  455Mbps  | 447Mbps | 502Mbps |
| rv-virt:netnsh64       |  602Mbps  |  595Mbps  | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp   |  414Mbps  |  515Mbps  | 491Mbps | 525Mbps |
| rv-virt:knetnsh64      |  515Mbps  |  457Mbps  | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp  |  308Mbps  |  389Mbps  | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
      Tested in QEMU 7.2.2

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-08-10 03:39:39 +08:00
Alan Carvalho de Assis
9914999715 stm32_qspi: Fix printf() format warnings 2023-08-09 11:06:23 +08:00
Petro Karashchenko
d113722eb2 style: fix indentation issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-08-08 11:58:29 -03:00
Petro Karashchenko
2c346c4c89 arch/esp32: use kernel internal API for libc stubs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-08-08 11:58:29 -03:00
xuxin19
4cd916d16b cmake:support armv7-r and tms570 chip
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-08-07 10:06:05 -07:00
wangming9
8d21bbf3be arch/armv8-m: Supports interrupt nesting between TEE and REE
The first time interrupt nesting occurs between REE and TEE,
CURRENT_REGS needs to be set.

If TEE nesting REE breaks, then EXC_RETURN.S=0,EXC_RETURN.ES=1;
Conversely, EXC_RETURN.S=1,EXC_RETURN.ES=0;
Interrupt nesting between TEE and REE can be determined based
on the S and ES bits of EXC_RETURN.
Only once nesting between TEE and REE is supported, and cyclic
nesting between TEE and REE is not supported.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
5cdfa6fec4 arch/armv8-m: Supports interrupt nesting
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
   The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack;

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
f8aaed780a arch/armv8-m: Add CONTROL register to xcptcontext.
To simplify the interrupt handling in protected mode.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
2684642a7a arch/armv6-m: Supports interrupt nesting
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
   The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack;

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
cedc034d9e arch/tlsr82: Port arm_doirq to tc32_doirq.c
Solve the dependency on ARMV6M when compiling tlsr8278adk80d:nsh.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
eba9c61cad arch/armv6-m: Add CONTROL register to xcptcontext.
To simplify the interrupt handling in protected mode.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
a4b6b158ce arch/armv6-m: By default, add REG_EXC_RETURN to xcptcontext.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
816b3fb399 arch/armv7-m: Supports interrupt nesting
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
   The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack,add arm_initialize_stack;

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
wangming9
4370487fd6 arch/armv7-m: Add CONTROL register to xcptcontext.
To simplify the interrupt handling in protected mode.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-08-07 05:43:13 -07:00
cuiziwei
c1ddfcfa83 nuttx/arch:support to obtain host cpuinfo in NSH. 2023-08-05 14:57:15 -07:00
Brennan Ashton
46b0f6d6ee fdt: Add initial FDT support and procfs for userspace export
VELAPLATFO-12536

This provides the initial hooks for Flattened Device Tree support
with QEMU RV. It also provides a new procfs file that exposes the
fdt to userspace much like the /sys/firmware/fdt endpoint in Linux.
See https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-firmware-ofw

Nodes in the fdt are not yet usable by the OS.

Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-08-05 12:41:06 -07:00
ligd
dfdb3aa2f4 armv8m: support busfault forward to TEE
For TEE & REE, securefault & busfault are not banked, so the faults can
only forword to TEE/REE.
But how to crash dump the other core which not handled faults ?

Here we provide a way to resolve this problem:
1. Set the securefault & busfault to TEE
2. busfault happend from TEE, then directly dump TEE
3. busfault happend from REE, then generate nonsecurefault
4. Back to REE, and dump

Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-05 12:40:34 -07:00
ligd
b445029cf2 armv8m: fix up_secure_irq failed for NVIC_IRQ_BUSFAULT
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-05 12:40:34 -07:00
ligd
452211586e xtensa: fix compile miss file
comiple xtensa_mpu.c

Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-05 12:40:16 -07:00
anjiahao
3a808bab19 support stm32f429i-disco run open flash loader
We can use the driver in nuttx to download
files with debugger

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: chao an <anchao@xiaomi.com>
2023-08-05 12:40:02 -07:00
Lucas Saavedra Vaz
d1b5558c8b arch/espressif: Add MCUboot support for ESP32-C3
Add MCUboot support for ESP32-C3 when using the Espressif HAL
2023-08-04 10:30:57 -07:00
Peter van der Perk
0b721ac21c imxrt: flexcan use hpwork for receiving frames
FlexCAN before used interrupts to process incoming frames.
This patch adds a HPWORK workqueue to process incoming frames in the workqueue
context instead. Also renamed mbi to txmb for better readability.
2023-08-04 19:28:52 +02:00
Lee Lup Yuen
856526adee arch/risc-v: Add support for StarFive JH7110 SoC
This PR adds support for the StarFive JH7110 RISC-V SoC. This will be used by the upcoming port of NuttX for PINE64 Star64 SBC. [The source files are explained in the articles here](https://github.com/lupyuen/nuttx-star64)

Modified Files in arch/risc-v:

Kconfig: Added ARCH_CHIP_JH7110 for JH7110 SoC

New Files in arch/risc-v:

include/jh7110/chip.h: JH7110 Definitions

include/jh7110/irq.h: Support 127 External Interrupts

src/jh7110/chip.h: Interrupt Stack Macro

src/jh7110/jh7110_allocateheap.c: Kernel Heap

src/jh7110/jh7110_head.S: Linux Header and Boot Code

src/jh7110/jh7110_irq.c: Configure Interrupts

src/jh7110/jh7110_irq_dispatch.c: Dispatch Interrupts

src/jh7110/jh7110_memorymap.h: Memory Map

src/jh7110/jh7110_mm_init.c, jh7110_mm_init.h: Memory Mgmt

src/jh7110/jh7110_pgalloc.c: Page Allocator

src/jh7110/jh7110_start.c: Startup Code

src/jh7110/jh7110_timerisr.c: Timer Interrupt

src/jh7110/hardware/jh7110_memorymap.h: PLIC Base Address

src/jh7110/hardware/jh7110_plic.h: PLIC Register Addresses

src/jh7110/Kconfig: JH7110 Config

src/jh7110/Make.defs: Makefile
2023-08-03 22:55:55 -07:00
yangsen5
d8ca744052 drivers/video: video driver supports NV12
Signed-off-by: yangsen5 <yangsen5@xiaomi.com>
2023-08-03 22:37:53 -07:00
yintao
5d1536c5e3 nuttx/sim: use workquene instead of sim_bthcisock_loop
Signed-off-by: yintao <yintao@xiaomi.com>
2023-08-03 21:15:36 -07:00
Fotis Panagiotopoulos
f3945560c0 stm32f4/f7/h7_eth: Improvements in Ethernet DMA error handling.
* Error handling for abnormal interrupts and DMA errors is now
enabled for all builds, regardless of any DEBUG configuration.

* Error handling resets the MAC for the specific errors that
may halt the Ethernet operation, instead of everything as it
was before.
2023-08-03 18:11:23 -03:00
ligd
af3600436e perf: avoid div zero if up_perf_init() hasn't init
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-03 10:42:00 -07:00
ligd
2cfea55f95 armv7-r: idle stack should align with 8
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-03 10:42:00 -07:00
ligd
f3063ce12b armv7-a: align stack_top code with armv7-r
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-03 10:42:00 -07:00
jianglianfang
d5a8746be8 sim framebuffer: Optimize the timing of window to open and to close
The window opens when the fb opens and closes when the fb closes.
test step: run fb demo, 1. ./nuttx 2. fb

Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
2023-08-03 10:36:17 -07:00
ligd
ebaea6bd9f sim: set loop thread priority to configurable
Signed-off-by: ligd <liguiding1@xiaomi.com>
2023-08-03 10:15:43 -07:00
simbit18
580d09b5a1 Fix Kconfig style
Remove spaces from Kconfig
2023-08-03 15:40:24 +02:00
zhangyuan21
79242cc1e7 arm64: set cpuid according to mpidr
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-03 03:19:19 -07:00
zhangyuan21
dc55205ee5 arch/arm64: get_cpu_id according to the correct affinity level
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-03 03:19:19 -07:00
yanghuatao
51240c658f fix warning: [-Wunknown-pragmas]
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:33: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   33 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:34: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   34 | #pragma clang diagnostic ignored "-Wpadded"
      |
In file included from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:4,
                 from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/IBase.h:4,
                 from android/hidl/base/1.0/BaseAll.cpp:1:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:40: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   40 | #pragma clang diagnostic pop
      |
In file included from /mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/IBase.h:4,
                 from android/hidl/base/1.0/BaseAll.cpp:1:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:188: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  188 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:189: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  189 | #pragma clang diagnostic ignored "-Wc++17-extensions"
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/android/hidl/base/1.0/types.h:195: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
  195 | #pragma clang diagnostic pop
      |
CXX:  LightRefBase.cpp In file included from base/HidlSupport.cpp:18:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:33: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   33 | #pragma clang diagnostic push
      |
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:34: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   34 | #pragma clang diagnostic ignored "-Wpadded"
      |
In file included from base/HidlSupport.cpp:18:
/mnt/yang/vela_keystore_waring/apps/external/android/system/libhidl/base/include/hidl/HidlSupport.h:40: warning: ignoring #pragma clang diagnostic [-Wunknown-pragmas]
   40 | #pragma clang diagnostic pop

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
2023-08-03 00:52:53 -07:00
yuexinyi
4f0a8dc391 drivers/video: fix if video node do not exist on host of sim env, video driver init fail
Signed-off-by: yuexinyi <yuexinyi@xiaomi.com>
2023-08-02 22:50:03 -07:00
Tiago Medicci Serrano
17447622bf esp32s3/wifi: support the Wi-Fi to work with protected build
- Added Wi-Fi related symbols to the kernel-space linker;
- Allocate more RAM to the kernel (to be useb by the Wi-Fi driver).
- Create a specific defconfig.
2023-08-02 21:38:44 +02:00
Tiago Medicci Serrano
1197a80741 esp32s3: Enhance protected build linker scripts and memory layout
Instead of setting kernel/user space instruction and data ROM as
hard-coded values on linker, set them according to the max size
of the kernel image set by CONFIG_ESP32S3_KERNEL_IMAGE_SIZE. This
is done by making KIROM, UIROM, KDROM and UDROM dependent on the
kernel size value. Also, override CONFIG_NUTTX_USERSPACE config
according to CONFIG_ESP32S3_KERNEL_IMAGE_SIZE by using a custom
PREBUILD definition.
2023-08-02 21:38:44 +02:00
raiden00pl
1d858ec03f stm32: initialize perf counter if sytemview enabled 2023-08-02 08:05:37 -07:00
simbit18
8ce16e9bd9 Fix Kconfig style
Remove spaces from Kconfig
2023-08-02 16:57:09 +02:00
Alan Carvalho de Assis
bace5e9b59 Fix some ESP32 Peripheral help comments 2023-08-02 05:40:42 -07:00
shipei
238eba14ad alsa/sim_alsa.c:fix ioctl AUDIOIOC_GETBUFFERINFO error
when executing ioctl AUDIOIOC_GETBUFFERINFO,the priv->pcm is still NULL,
so it will return -ENXIO,we can remove this check at the start of ioctl
and add in the case where it is used.

Signed-off-by: shipei <shipei@xiaomi.com>
2023-08-02 03:27:12 -07:00
Peter van der Perk
2e3c144f44 imxrt: fix txdeadline add ecc/fd support 2023-08-01 10:10:41 -07:00
zhangyuan21
8f39ba6ae4 arch: update g_running_tasks when context switch occurred
When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-08-01 09:35:18 -07:00
lpxiao
3341a6d2a9 Optimize stm32 RTC accuracy 2023-08-01 18:02:09 +02:00
Petro Karashchenko
f00c6d3047 arch/arm: fix declaration of extern types
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-07-31 18:56:40 -07:00
yangyalei
fde8affe71 singal: add stack_t define
stack_t used by sigaltstack, make it compile sucess in sim.

Signed-off-by: yangyalei <yangyalei@xiaomi.com>

ltp: fix compile errors

Signed-off-by: yangyalei <yangyalei@xiaomi.com>
2023-07-31 07:50:10 -07:00
Ville Juven
61460efe3c riscv/qemu-rv: Add FPU support back to qemu-rv
The FPU restore issue does not show itself any longer, so FPU support
can be re-enabled.
2023-07-31 07:48:53 -07:00
Ville Juven
d0fbf9883d riscv/lazyfpu: Add option to disable lazy FPU
Adds option to use the old implementation where FPU is stored into
the process stack.
2023-07-31 07:48:53 -07:00
Ville Juven
4a468b8d3b riscv/saveusercontext: Fix FPU state save 2023-07-31 07:48:53 -07:00
Ville Juven
0ea9debfce riscv/riscv_fpu: Clear the full FPU status/control register on boot
Instead of clearing the fields individually, just wipe the whole register.
This can be done because flags and rm are just parts of the fcsr.

31             8        5           0
+--------------+--------+-----------+
|              |        |           |
|   RESERVED   |  FRM   |  FSTATUS  |
|              |        |           |
+--------------+--------+-----------+
                FCSR
2023-07-31 07:48:53 -07:00
Ville Juven
b409d72e9d riscv/fpu: Restore correct lazy-FPU functionality
- Save the FPU registers into the tcb so they don't get lost if the stack
  frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
  - Save ONLY if FPU is dirty
  - Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
2023-07-31 07:48:53 -07:00
Ville Juven
3b5c0c885f riscv/swint: Give the full tcb to the context switch routine
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.

Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
2023-07-31 07:48:53 -07:00
Bowen Wang
28cb5e7984 arm64: add kasan support for arm64
Add kasan compiler option in arm64 Toolchain.defs

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2023-07-31 05:45:46 -07:00
zhangyuan21
f9cab5b9dc arch/arm64: add ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE config
Enable dcache and icache when ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE
disabled at __start.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-31 05:33:23 -07:00
Bowen Wang
d24622888f arm64_backtrace: use running_task if arch_get_current_tcb return NULL
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2023-07-31 04:52:49 -07:00
zhangyuan21
c6f32f4363 arm-m: Check the dcache status before enabling dcache
If the cache is already enabled before NuttX starts up,
enabling the cache in NuttX will cause the cache to be
re-invalidated, then resulting in data that is already
in the cache being flushed out.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-07-31 08:49:21 +02:00
Xiang Xiao
fc5e85da1b drivers: Format pointer through "%p" for kthread_create
to remove the unnecessary cast and unify the usage

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-07-30 23:40:59 +03:00
yuexinyi
56be0ab050 drivers/video: add capture arg to support multi instance
Signed-off-by: yuexinyi <yuexinyi@xiaomi.com>
2023-07-29 07:42:29 -07:00
hujun5
e3f481d3b1 arm/trustzone: time interrupt setting failed
we should use a secure clock when the CPU is in secure mode

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-07-29 06:58:24 -07:00
dongjiuzhu1
d89e0996f5 sim/usbdev: Add string table as it is needed when USBTRACE is turned on
nuttx/drivers/usbdev/usbdev_trprintf.c:418: undefined reference to `g_usb_trace_strings_intdecode'
/usr/bin/ld: nuttx/drivers/usbdev/usbdev_trprintf.c:496: undefined reference to `g_usb_trace_strings_deverror'

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-07-28 20:58:23 -07:00
dongjiuzhu1
ddc2c62aa8 sim/rawgadget: don't push fifo if ioctl failed because it will cause busy read
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-07-28 20:58:23 -07:00
dongjiuzhu1
14446677d3 arch/arm64: default select ARCH_HAVE_SETJMP
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-07-28 20:57:26 -07:00
dongjiuzhu1
7d281f46de sim/hostfs: fix issue about access file with size more than 2GB
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-07-28 07:42:12 -07:00
Tiago Medicci Serrano
8673e659b4 espressif: quiet git commands and improve build logging
Add `--quiet` to git commands to avoid unnecessary logging during
the operation and add summarized logs to show progress.
2023-07-27 19:43:48 -07:00
Tiago Medicci Serrano
e38b4b2103 espressif: fix linker to include the reserved area of RTC memory
Basically, it reserves an area of the RTC memory to preserve the
RTC timer.

Please refer to:
fa76c82a5b

This commit also removes the rtc.dummy section because C3, C6 and
H2 don't need to skip it once the region is accessed by the same
address space using the instruction and data bus.
2023-07-27 19:43:48 -07:00