This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:
- Support for Setup Out packets
- Proper support for larger than packet size writes
- Finishing setup packets properly
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
usbmsc.h uses the CONFIG_USBMSC_IFNOBASE configuration option,
but it cannot be set anywhere. Provide means to configure this
option which is useful when it's other than the default zero.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Output "X" with showprogress and make a system reset.
Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This patch adds documentation for both stm32wl5 chip family and
nucleo-wl55jc board. I've kept the same directory structure for
arm/stm32 as in arch/ and boards/ directories.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Multiple files were badly formatted, which resulted in many
warnings. This made it harder to check for errors in newly
written documentation.
What's worse, badly formatted text resulted in butchered
output in generated html.
This patch fixes most of the errors, but alas, not all of
the errors can be fixed. Anyway, this should be way easier
to spot errors in newly written docs now.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
since devif_timer has been removed in:
commit 035d925864
Author: zhanghongyu <zhanghongyu@xiaomi.com>
Date: Sun May 29 21:47:28 2022 +0800
devif: remove all devif_timer
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This patch includes bare minimum support for nucleo-wl55jc board.
It compiles and nsh shell is working properly on virtual com port
over USB. 3 onboard leds with userled driver are working.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
This patch adds new chip family, stm32wl5x. This is bare minimum
implementation of said chip. I've tested this by running nsh.
There are only two chips in this family, stm32wl55 and stm32wl54.
The only difference between them is that stm32wl55 has LORA.
stm32wl5 is dual CPU (not core!). Right now only CPU1 is implemented.
CPU0 has access to radio hardware (while CPU1 does not). Chip is
designed so that CPU0 handles radio traffic while CPU1 does the
heavy lifting with data - there is communication pipe between two
CPUs.
I plan to use nuttx on CPU1 and LORA from stm32cube on CPU0 so I
don't have implementing CPU0 right now - once we have working LORA
in nuttx this may change.
Peripherals (except for radio) are shared so it's best to focus on
CPU1 to initialize all peripherals so that CPU0 can only use them
later. There is no real benefit to implement CPU0 if we don't have
working LORA/radio support in nuttx.
In time I will be implementing more and more things from this chip.
Right now I would like this minimal implementation to be merged in
case someone wants to work on this chip as well.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
---
patch v1->v2
- fixed formatting (suggested by Alan Carvalho de Assis)
- rebased patch to master (previous patch was based on nuttx-10.2
and did not compile on master)
arch/x86/Kconfig:28:warning: choice value used outside its choice group
arch/x86/Kconfig:29:warning: defaults for choice values not supported
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
We might have a situation where an allocation will be requested before
the call to `up_initialize` is performed. For the current code, this
situation is the stack for the CPUs in SMP mode.
Beside this issue, it's natural to have the internal heap initialized
with the other heaps.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
