Add ARCH_CHIP_QEMU_TRUSTZONE to enable/disable the TrustZone
support beacause qemu also support enable/disable Arm Security
Extensions: https://qemu-project.gitlab.io/qemu/system/arm/virt.html
when launch.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
since gcc report the false alarm if the pointer offset from zero address:
inlined from 'up_vectormapping' at chip/dm320_boot.c:162:7,
inlined from 'arm_boot' at chip/dm320_boot.c:211:3:
Error: chip/dm320_boot.c:117:17: error: array subscript 0 is outside array bounds of 'uint32_t[0]' {aka 'long unsigned int[]'} [-Werror=array-bounds=]
117 | ctable[index] = (paddr | mmuflags);
| ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The `xxx_ipv6multicast` function in each driver is not adapted to
multiple IPv6 addresses yet, and they're redundant, so try to take them
into common code.
Change:
1. Add MAC `g_ipv6_ethallnodes` and `g_ipv6_ethallrouters` in
`icmpv6_devinit` and call them in `netdev_register`
2. Add multicast MAC for Neighbor Solicitation when adding any IPv6
address, and remove them when IPv6 address is removed
3. Select `NET_MCASTGROUP` when `NET_ICMPv6` because now we need
`d_addmac` when we have ICMPv6
Note:
We want modules outside net stack to call functions like
`netdev_ipv6_add` and never touch the related MAC address, so these MAC
functions are added as internal functions to `net/netdev/netdev.h`
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
The ADC peripheral can only support up to
50MHz on rev V silicon and 36MHz on Y silicon.
The existing driver always used no prescaler
and kept boost setting at 0.
The 1170 usage of the GPR registers is to select the
between GPIO{2|3} or CM7_GPIO{2|3} where as the 1060
it selected ports between 1-6,2-7..4-9 and uses
different GPR registers.
For the 1170 we are defaulting to GPIO{2|3} and not
supporting the swtich to CM7_GPIO{2|3}.
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
Co-authored-by: David Sidrane <david.sidrane@nscdg.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
imxrt:Kconfig fix formatting
imxrt:usbphy move IMXRT_USBPHY{1|[2]}_BASE to memory map
imxrt:lpspi Fix build breakage from adding 1170
imxrt:Finish 1170 iomux and clockconfig versioning
imxrt:Remove duplicate imxrt_clock{off|all}_lpi2c4
imxrt:pmu remove duplicate dcd non 117x header
imxrt:lpspi Fix unused var warnings
imxrt:lpi2c Fix unused var warnings
imxrt:lowputs Fix unused var warnings
imxrt:imxrt117x_dmamux fix duplicate entries
imxtr:serial Use IOMUX_PULL_{UP|DOWN} and map IOMUX V1 to them
imxrt:MPU Support the 1170
imxrt:dmamux Alias IMXRT_DMAMUX0_BASE as IMXRT_DMAMUX_BASE
imx1170:ccm Alias CCM_CCGR_DMA & CCM_CCGR_SNVS_LP for compatiblity
Author: Peter van der Perk <peter.vanderperk@nxp.com>
IMXRT7 Add LPUART 9/10/11/12 support
Author: David Sidrane <david.sidrane@nscdg.com>
imxrt:1170pinmux Add QTIMER pins
imxrt:1170pinmux Add GPT pins
imxrt:1170pinmux Add FLEXPWM pins
imxrt1170:pinmap Add GPIO_ENET_1G pinning
imxrt:enet Support ENET_1G
imxrt:periphclks rt1170 does not have canX_serial clock
imxrt:flexcan:Layer imxrt_ioctl
imxrt117x:memorymap added CAN3
imxrt:ADC support ver1 and ver2 for imxrt117x
imxrt:imxrt117x_ccm Align timer naming with other imxrt QTIMERn->TIMERn
imxrt:imxrt117x_ccm align CCM names with rt106x
imxrt:XBAR support larger number of selects needed on imxrt1170
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
FlexSPI AHB Region support, PIT rename for compatiblity
imxrt:USB Analog add VBUS_VALID_3V
FlexSPI expand prefetch registers for IMXRT117X
imxrt:Support Initialization of FlexRam without Running from OCRAM
imxrt: ocotp add UNIQUE_ID register definition
imxrt: enet use ocotp unique_id
imxrt: enet fixes for imxrt117x
imxrt: ethernet pinmux sion enable
imxrt:imxrt_periphclk_configure add memory sync
Flush the pipeline to prevent bus faults, by insuring a
peripheral is clocked before being accessed on return from
this function.
imxrt:Restructure gpioN to padmux mapping
imxrt:Add imxrt1170 daisy
imxrt: correct power modes for imxrt117x fixing hang on WFI
imxrt: imxrt117x TCM MPU config
imxrt: FlexRAM clocking DIV0 setup
imxrt: 117x periphclocks wait for status bit
imxrt: iomucx set pad settings correctly and allow reconfiguration
imxrt: enet align buffers 64-byte for optimal performance
Add DSC barriers for write-through cache support
imxrt: imxrt1170 use FlexCAN FD/ECC features
imxrt:iomuxc_ver2 (117x) SD_B1 and DISP_B1 use PULL feild not PUE/PUS
imxrt:Fix 1170 SNVS addressing
imxrt: enet set mii clock after ifdown so that phy keep working
nxstyle fixes
imxrt: preprocessor and include fixes
Fix configs
imxrt1170-evk clean defconfig
Fixes is stuttering output.
The use of the semaphore was causing blocking
on non blocking callers. This ensured that
the TX DAM would be restated, but when it
was switched to trywait in 660ac6, it left
data in the xmit queue unsent.
This solution removes the semaphore and restart
the DMA on completion if there is more data in
the xmit queue to be sent.
chip/sam_emac.c:3754:11: error: 'struct sam_emac_s' has no member
named 'phytype'
3754 | if (priv->phytype == SAMV7_PHY_KSZ8061)
| ^~
make[3]: *** [Makefile:167: sam_emac.o] Error 1
Member phytype is available only if CONFIG_NETDEV_PHY_IOCTL and
CONFIG_ARCH_PHY_INTERRUPT is set.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Fixes stuttering output.
The use of the semaphore was causing blocking
on non blocking callers. This ensured that
the TX DAM would be restated, but when it
was switched to trywait in 8362e314, it left
data in the xmit queue unsent.
This solution removes the semaphore and restart
the DMA on completion if there is more data in
the xmit queue to be sent.
This prevents dma stop operations called of a completion
call back from rentering, the callback and ensures that
the call back will see the idle state.
Since picolibc used by clang-17 does not provide an implementation of libm,
if you want to use clang, please must specify a libm as an option.
Signed-off-by: chao an <anchao@xiaomi.com>
armv6-m/arm_dumpnvic.c: In function 'arm_dumpnvic':
armv6-m/arm_dumpnvic.c:67:13: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'uint32_t' {aka 'long unsigned int'} [-Wformat=]
67 | _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv6-m/arm_dumpnvic.c:67:27: note: format string is defined here
67 | _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
| ~~~^
| |
| unsigned int
| %08lx
Signed-off-by: chao an <anchao@xiaomi.com>
chip/stm32_ethernet.c:2014:7: warning: variable 'i' set but not used [-Wunused-but-set-variable]
2014 | int i;
| ^
1 warning generated.
Signed-off-by: chao an <anchao@xiaomi.com>
To avoid losing the first frame, the set_buf needs to excute first. At the same time, imgdata->start_capture should excuted before the imgsensor->start_capture.
Signed-off-by: yaojingwei <yaojingwei@xiaomi.com>
Adds support for hardware timestamping of received Ethernet packets.
The timestamp is available to applications using socket option SO_TIMESTAMP.
Optionally, the Ethernet PTP timer can be used as system high-resolution RTC.
In this mode it supports fine resolution rate adjustment.
Alternatively other time source for CLOCK_REALTIME can be used, and the
PTP timestamps are converted by sampling the clocks and computing the
difference. This results in a few microseconds of uncertainty.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be
blocked forever on the second transmit attempt due to waiting
on the txdma semaphore. The calling thread can then never
make progress and release any resources it has taken, thus
may cause a deadlock in other parts of the system.
The implementation differs in behavior from interrupt-driven
TX. It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to
do next.
If using flow control with a high CTS the thread may be blocked forever
on the second transmit attempt due to waiting on the txdma semaphore.
The calling thread can then never make progress and release any
resources it has taken, thus may cause a deadlock in other parts of the
system.
The implementation differs in behavior from interrupt-driven TX and the
STM32F7 TXDMA . It should not implicitly wait on a taken semaphore but
return immediately and let the upper layers decide on what to do next.
Some APIs are implemented both in common code and CHIP-specific code,
and the link needs to be based on the implementation in CHIP, so move
NUTTX_CHIP_ABS_DIR before common src.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
These flags are not used in the code.
SERIAL_HAVE_RXDMA and SERIAL_HAVE_TXDMA flags are used instead.
STM32_UART_TXDMA flag is not even defined in Kconfig
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With TCD set to loop, there is a window where the
DMA has raised Done, but not reloaded the TCD, resetting
count and clearing Done.
In this window imxrt_dmach_getcount could then return 0.
Resulting in imxrt_dma_nextrx returning RXDMA_BUFFER_SIZE.
Which is not a valid index in the FIFO.
Since the count will be set to RXDMA_BUFFER_SIZE. When the DMA
engine completes the TCD reload. The imxrt_dma_nextrx would
return 0. Therefore:
(RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE
accomplishes this.
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
With DMA enabled on some I2C channels but not all
the Non DMA channels were failing.
The cause was condition the status with only the enabled
interrupts on non DMA chennels. This conditioning needs
to only happen in DMA enabled channels
The DMA can bring in more rx data, than the number of
DMA completions call backs. The call back happen on
idle, 1/2 and full events. But in between these events
the DMA can write more data to the buffers memory that
need to be brought in to the cache. (invalidate)
We do the invalidate on the reads from the fifo memory
if the the DMA as commited since the last read.
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):
```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```
This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.
This PR proposes to change `sed -r` to `sed -E` because:
- `sed -E` on macOS is equivalent to `sed -r` on Linux
- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual
- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
stm32_ifdown() holds critical section when calling stm32_ethreset().
That function used to call up_mdelay(10) while waiting for the ethernet
peripheral reset to complete. This resulted in excessively long
critical section time with interrupts disabled.
The actual expected delay is a few clock ticks of the 50 MHz clock domain.
This commit changes polling interval to 1us and maximum to 10us.
This commit adds support for 1 wire interface over serial driver. SAMv7
MCU does not have build in one wire support therefore external hardware
still has to be used (connection of RX/TX for example).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
UART/USART peripheral can be used for more than just standard serial
driver. It can for example be used for 1 wire interface communication
(with external circuitry added). This changes the Kconfig for SAMv7 to
allow future implementation of these drivers. Now user can select
what kind of a driver he wants on UART/USART (serial or something else).
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
When unwind instruction is 0xb2,the subsequent instructions
are uleb128 bytes.
For now,it uses only the first uleb128 byte in code.
For vsp increments of 0x204~0x400,use one uleb128 byte like below:
0xc06a00e4 <unwind_test_work>: 0x80b27fac
Compact model index: 0
0xb2 0x7f vsp = vsp + 1024
0xac pop {r4, r5, r6, r7, r8, r14}
For vsp increments larger than 0x400,use two uleb128 bytes like below:
0xc06a00e4 <unwind_test_work>: @0xc0cc9e0c
Compact model index: 1
0xb2 0x81 0x01 vsp = vsp + 1032
0xac pop {r4, r5, r6, r7, r8, r14}
The unwind works well since the decoded uleb128 byte is also 0x81.
For vsp increments larger than 0x600,use two uleb128 bytes like below:
0xc06a00e4 <unwind_test_work>: @0xc0cc9e0c
Compact model index: 1
0xb2 0x81 0x02 vsp = vsp + 1544
0xac pop {r4, r5, r6, r7, r8, r14}
In this case,the decoded uleb128 result is 0x101(vsp=0x204+(0x101<<2)).
While the uleb128 used in code is 0x81(vsp=0x204+(0x81<<2)).
The unwind aborts at this frame since it gets incorrect vsp.
To fix this, add uleb128 decode to cover all the above case.
Signed-off-by: chao an <anchao@xiaomi.com>
Summary
include/arch/syscall.h: Assembler messages:
include/arch/syscall.h:133: Error: bad instruction `struct arm_smccc_res'
include/arch/syscall.h:134: Error: junk at end of line, first unrecognized character is `{'
include/arch/syscall.h:135: Error: bad instruction `unsigned long a0'
include/arch/syscall.h:136: Error: bad instruction `unsigned long a1'
include/arch/syscall.h:137: Error: bad instruction `unsigned long a2'
include/arch/syscall.h:138: Error: bad instruction `unsigned long a3'
include/arch/syscall.h:139: Error: bad instruction `unsigned long a4'
include/arch/syscall.h:140: Error: bad instruction `unsigned long a5'
include/arch/syscall.h:141: Error: bad instruction `unsigned long a6'
include/arch/syscall.h:142: Error: bad instruction `unsigned long a7'
include/arch/syscall.h:143: Error: junk at end of line, first unrecognized character is `}'
include/arch/syscall.h:145: Error: bad instruction `typedef struct arm_smccc_res
Signed-off-by: wangming9 <wangming9@xiaomi.com>
The typo s/.timid/.tcid prevents to compile NuttX with
quadrature encoder configured for timer1 (CONFIG_SAMV7_TC1_QE)
and s/SAM_TC789_BASE/SAM_TC678_BASE prevented use of the
of the timer 2.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android
enhance it with more featue.
The patch set goldfish as a arm chip.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This change fixes the issue when SAMv7 GMAC sometimes does not start packet
transmission. The issue is that EMAC_NCR_TSTART is written to EMAC_NCR register
while tx descriptor is not delivered to memory.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
According to the current implementation, "cxd56_cpu1siguninit" will only
be called once during the NuttX startup phase,
and it won't involve scenarios of multi-threaded concurrent access.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).
This commit adds CD/DAT3 line card detection support for SAMv7 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds function pwm_set_polarity() that setups channel
polarity based on input info from application layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
After sevaral resets of the chip after programming, rptun stops working correctly.
Simple test with RPMSG UART causes a lock:
on the netcore:
nsh>cat /dev/ttyproxy
on the appcore:
nsh>echo xxx > /dev/ttyproxy
The problem doesn't occur with NRF53_FLASH_PREFETCH=n
after the follow patch:
commit 9aa57b6c53
Author: wangbowen6 <wangbowen6@xiaomi.com>
Date: Wed Mar 22 11:49:43 2023 +0800
virtio: add virtio framework in NuttX
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
(IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
support mmio transport layer, and the new framwork support
more transport layer and this commit has implemented all the
old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
configs, and update its README.txt;
New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
| | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh | 539Mbps | 524Mbps | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp | 401Mbps | 437Mbps | 583Mbps | 505Mbps |
| rv-virt:netnsh | 487Mbps | 512Mbps | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp | 387Mbps | 455Mbps | 447Mbps | 502Mbps |
| rv-virt:netnsh64 | 602Mbps | 595Mbps | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp | 414Mbps | 515Mbps | 491Mbps | 525Mbps |
| rv-virt:knetnsh64 | 515Mbps | 457Mbps | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp | 308Mbps | 389Mbps | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
Tested in QEMU 7.2.2
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
(1)common/arm_backtrace_unwind.c:528:18: warning: 'ctrl.lr_addr' may be used uninitialized in this function [-Wmaybe-uninitialized]
(2)common/arm_backtrace_unwind.c:626:27: warning: assignment to 'long unsigned int' from 'uint8_t (*)[]' {aka 'unsigned char (*)[]'} makes integer from pointer without a cast [-Wint-conversion]
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting，solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.
This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion
To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization
Signed-off-by: wangming9 <wangming9@xiaomi.com>
