Commit Graph

45105 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
8a215b60af libcxx: Add patch for preventing redefinition of PS macro on Xtensa
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
06d0a9f1ad xtensa|risc-v: Make CXX exception and RTTI depend on Kconfig options
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
a0617177e8 risc-v/esp32c3: Fix inclusion of C++ constructors/destructors table
RISC-V GCC is configured with --enable-initfini-array so it emits an
.init_array section instead of .ctors

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
c7311829e0 xtensa: Build OS-assisted atomic operations on ESP32-S2
ESP32-S2 lacks support for conditional load/store instructions.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Gustavo Henrique Nihei
7926bce26b xtensa: Move XCHAL_SWINT_CALL definition into syscall header
This is required to avoid the interface header (syscall.h) depending on
the xtensa_swi.h header from the implementation

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-30 11:19:29 +08:00
Lee Lup Yuen
416ec42077 riscv/esp32c3: Remove check for LCD driver
## Summary

`esp32c3_spi2_cmddata()` implements SPI Cmd/Data `SPI_CMDDATA()` for only 3 LCD drivers: ST7735, ST7789 and GC9A01.

This patch removes the check for LCD drivers, so that SPI Cmd/Data will work for all LCD drivers.

More details: https://github.com/apache/incubator-nuttx/pull/5898

## Impact

This change impacts LCD drivers that call `SPI_CMDDATA()`.

Previously `SPI_CMDDATA()` would fail with `ENODEV` for LCD drivers other than ST7735, ST7789 and GC9A01.

After patching, `SPI_CMDDATA()` will work correctly with all LCD drivers.

## Testing

This is a minor patch so no testing is needed.
2022-03-29 23:09:57 -03:00
Lee Lup Yuen
4456b13c19 riscv/bl602: Remove check for LCD driver
## Summary

`bl602_spi_cmddata()` implements SPI Cmd/Data `SPI_CMDDATA()` for only 3 LCD drivers: ST7735, ST7789 and GC9A01.

This patch removes the check for LCD drivers, so that SPI Cmd/Data will work for all LCD drivers.

More details: https://github.com/apache/incubator-nuttx/pull/5898

## Impact

This change impacts LCD drivers that call `SPI_CMDDATA()`.

Previously `SPI_CMDDATA()` would fail with `ENODEV` for LCD drivers other than ST7735, ST7789 and GC9A01.

After patching, `SPI_CMDDATA()` will work correctly with all LCD drivers.

## Testing

We tested with LVGL and ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-30)
2022-03-29 23:09:42 -03:00
ligd
e9f17947b7 task: don't set default signal in kernal thread
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-30 10:53:14 +09:00
ligd
0c1f63625a signal: Don't do schedule_sigaction when there is no action
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-30 10:53:14 +09:00
chao.an
a98a599cb9 arm/cortex-[a|r]: IRQ Switch return should with shadow SPSR
The SPSR is used to store the current value of the CPSR when an exception
is taken so that it can be restored after handling the exception.
Each exception handling mode can access its own SPSR.

User mode and System mode do not have an SPSR because they are not
exception handling modes.

Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-30 08:12:26 +09:00
ligd
b0e0f9db68 opendir: use inode_find() instead when opendir()
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-30 03:33:39 +08:00
Richard Tucker
dc93c309b5 boards/risc-v/litex/arty_a7: update README to include building in LITESDCARD peripheral 2022-03-30 02:35:27 +08:00
Richard Tucker
3939575d7c boards/risc-v/litex/arty_a7: add SDCARD support for the Arty_A7 board 2022-03-30 02:35:27 +08:00
Richard Tucker
6d8cd4ec92 arch/risc-v/src/litex/litex_sdio: add litesdcard peripheral driver
See the following for details on the pepheral:
https://github.com/enjoy-digital/litesdcard
2022-03-30 02:35:27 +08:00
Richard Tucker
163e3fd93c driver/mmcsd: add option to support SD/MMC PHYs that only run in 4-bit mode 2022-03-30 02:35:27 +08:00
Richard Tucker
d557b87b25 arch/risc-v/litex: add cache_invalidate 2022-03-30 02:35:27 +08:00
Lee Lup Yuen
4f885fe6bf riscv/bl602: Implement SPI Cmd/Data
## Summary

To control the Data/Command Pin on ST7789 SPI Display, the SPI Driver flips the MISO Pin as though it was a GPIO.

To implement this on BL602, we reconfigure MISO from SPI Pin to GPIO Pin on the fly inside `bl602_spi_cmddata()`.

When the SPI Port is deselected (after the SPI operation), we revert MISO back from GPIO Pin to SPI Pin. We implement this inside `bl602_spi_select()`.

[More Details Here](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

## Impact

This change impacts 3 LCD drivers that call `SPI_CMDDATA()`: ST7735, ST7789, GC9A01.

Previously the BL602 SPI Driver would fail with "SPI cmddata not supported" when the above drivers are used.

After the change, the above drivers will set the LCD Data/Command Pin correctly.

## Testing

We tested this implementation of SPI Cmd/Data with NuttX ST7789 Driver and a Logic Analyser on PineCone BL602:

-   [Testing with Logic Analyser](https://github.com/lupyuen/st7789-nuttx#spi-cmddata)

We also tested LVGL with ST7789 on PineCone BL602:

-   [Testing with LVGL](https://github.com/lupyuen/st7789-nuttx#run-lvgl-demo)

As for regular SPI Devices that don't require SPI Cmd/Data, we tested `CONFIG_SPI_CMDDATA=y` with Semtech SX1262 SPI Transceiver on PineCone BL602:

-   [Testing Cmd/Data](https://github.com/lupyuen/incubator-nuttx/releases/tag/release-2022-03-29)
2022-03-30 02:01:29 +08:00
Huang Qi
904f7aabda arch/risc-v: Use riscv_fpuconfig to enable FPU
Use common function instead of chip specified code.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
Huang Qi
20c511fcf1 arch/risc-v: Rename up_fpuconfig to riscv_fpuconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-30 01:33:04 +08:00
ligd
d09be7d658 workqueue: add work_foreach support
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 18:03:08 +08:00
tianxin7
b53bbb15c5 fs:add _POSIX_OPEN_MAX limit to files_extend
Signed-off-by: 田昕 <tianxin7@xiaomi.com>
2022-03-29 17:51:20 +08:00
zhuyanlin
0460367a70 irq_csection: fix assert warning
constant 65535 with expression of type 'int16_t' (aka 'short')
is always true

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-29 13:44:01 +08:00
ligd
7619d2a6f9 syslog: fix syslog print twice when active assert
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 12:20:37 +08:00
ligd
b6e0614be6 syslog: use & instead of % when calculate offset
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 12:20:37 +08:00
ligd
61cb79d192 syslog_rpmsg: change head & tail NON-wrap
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 12:20:37 +08:00
Petro Karashchenko
f5665db1f2 boards: correct path to RCRAWS files during file copy
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-03-29 12:11:09 +08:00
Xiang Xiao
37d7298f34 fs/littlefs: Convert the lfs_file_size error code to POSIX's
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-03-29 10:11:13 +08:00
Jiuzhu Dong
1146ff2f61 littlefs: unify lfs error code to nuttx
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-03-29 10:11:13 +08:00
ligd
ed8704d90e sim/rptun: rsc must set rpmsg_vdev.config_len
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 10:10:33 +08:00
ligd
1796663e08 rpmsg_socket: fix kasan report error
==1598322==ERROR: AddressSanitizer: heap-use-after-free on address 0xf514f8a8 at pc 0x58ac3898 bp 0xd0b4d488 sp 0xd0b4d478
READ of size 4 at 0xf514f8a8 thread T0
    #0 0x58ac3897 in rpmsg_socket_pollnotify rpmsg/rpmsg_sockif.c:211
    #1 0x58ac512f in rpmsg_socket_ept_cb rpmsg/rpmsg_sockif.c:312
    #2 0x5787881c in rpmsg_virtio_rx_callback open-amp/lib/rpmsg/rpmsg_virtio.c:331
    #3 0x57886a67 in virtqueue_notification open-amp/lib/virtio/virtqueue.c:623
    #4 0x5786fb89 in rproc_virtio_notified open-amp/lib/remoteproc/remoteproc_virtio.c:340
    #5 0x5786bde3 in remoteproc_get_notification open-amp/lib/remoteproc/remoteproc.c:985
    #6 0x57755a50 in rptun_worker rptun/rptun.c:303
    #7 0x57755e51 in rptun_thread rptun/rptun.c:352
    #8 0x57730d4a in nxtask_start task/task_start.c:128
    #9 0xdeadbeee  (/memfd:pulseaudio (deleted)+0x15dbeee)

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 10:09:49 +08:00
ligd
a1eb3f66fa rexec: fix free error in error handing
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-29 10:09:04 +08:00
Jiuzhu Dong
66d854371b fs/files_allocate: assert when fd overflow
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-03-29 00:19:13 +08:00
ligd
ad9ba8f454 local_socket: default set block mode if accept() a new socket
reference:
https: //man7.org/linux/man-pages/man2/accept.2.html

1. default set block mode if accept() a new socket
2. local_socket support FIONBIO

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-28 23:26:34 +08:00
ligd
5b027f5260 net: netdev_ioctl handle FIONBIO
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-28 23:26:34 +08:00
zhuyanlin
d7391bf6bc xtensa: add xtensa arch oneshot ops
As xtensa timer is common in all xtensa chips,
Use oneshot ops, implement a common xtensa oneshot timer.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-28 22:55:00 +08:00
ligd
0f02791ae6 armv8-m: add wake_func arm_should_generate_nonsecure_busfault
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-28 22:52:28 +08:00
ligd
60fc933261 armv8-m: make the securefault handled by non-securefult
tee is secure cpu and ap is non-secure cpu.
The crash PC can get by IP (R12).

[ EMERG] [tee] arm_hardfault: Hard Fault escalation:
[ EMERG] [tee] arm_securefault: PANIC!!! Secure Fault:
[ EMERG] [tee] arm_securefault:         IRQ: 3 regs: 0x2400ff00
[ EMERG] [tee] arm_securefault:         BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000003 CONTROL: 0000000c
[ EMERG] [tee] arm_securefault:         CFSR: 00000000 HFSR: 40000000 DFSR: 00000000
[ EMERG] [tee] arm_securefault:         BFAR: 08006008 AFSR: 00000000 SFAR: 3c049ea0
[ EMERG] [tee] arm_securefault: Secure Fault Reason:
[ EMERG] [tee] arm_securefault:         Attribution unit violation
[ EMERG] [tee] arm_securefault_handled_by_ns: Non-sec sp 3c475678
[ EMERG] [ap] arm_busfault: PANIC!!! Bus Fault:
[ EMERG] [ap] arm_busfault:     IRQ: 5 regs: 0x3c475608
[ EMERG] [ap] arm_busfault:     BASEPRI: 000000e0 PRIMASK: 00000000 IPSR: 00000005 CONTROL: 00000004
[ EMERG] [ap] arm_busfault:     CFSR: 00000100 HFSR: 40000000 DFSR: 00000000 BFAR: 08006008 AFSR: 20000000
[ EMERG] [ap] arm_busfault: Bus Fault Reason:
[ EMERG] [ap] arm_busfault:     Instruction bus error
[ EMERG] [ap] up_assert: Assertion failed at file:armv8-m/arm_busfault.c line: 105 task: nsh_main
[ EMERG] [ap] backtrace:
[ EMERG] [ap] [ 9] [<0x2c565246>] up_backtrace+0xa/0x168
[ EMERG] [ap] [ 9] [<0x2c550118>] sched_dumpstack+0x1c/0x60
[ EMERG] [ap] [ 9] [<0x2c5645d6>] up_assert+0x4e/0x324
[ EMERG] [ap] [ 9] [<0x2c54a98e>] _assert+0x2/0x10
[ EMERG] [ap] [ 9] [<0x2c5636d4>] arm_busfault+0xc8/0x15c
[ EMERG] [ap] [ 9] [<0x2c523070>] irq_dispatch+0x40/0x11c
[ EMERG] [ap] [ 9] [<0x2c563424>] arm_doirq+0x28/0x3c
[ EMERG] [ap] [ 9] [<0x2c55c892>] exception_common+0x4a/0xac
[ EMERG] [ap] [ 9] [<0x2c58668e>] nsh_parse_command+0x976/0x12b4
[ EMERG] [ap] [ 9] [<0x2c849cee>] write+0x52/0x74
[ EMERG] [ap] [ 9] [<0x2c58c0ac>] nsh_session+0x2c/0x1c8
[ EMERG] [ap] [ 9] [<0x2c58d82c>] nsh_consolemain+0x28/0x54
[ EMERG] [ap] [ 9] [<0x2c590352>] nsh_main+0x2a/0x48
[ EMERG] [ap] [ 9] [<0x2c5500da>] cxx_initialize+0x2a/0x4c
[ EMERG] [ap] [ 9] [<0x2c550090>] nxtask_startup+0x14/0x34
[ EMERG] [ap] [ 9] [<0x2c52966a>] nxtask_start+0x92/0xb8
[ EMERG] [ap] arm_registerdump: R0: 3c049ea0 R1: 00000004 R2: 3c448f98  R3: 00000000
[ EMERG] [ap] arm_registerdump: R4: 3c476a98 R5: 3c049ea0 R6: 00000000  FP: 3c476aac
[ EMERG] [ap] arm_registerdump: R8: 2c5873c9 SB: 3c049ea0 SL: 3c2e98fc R11: 3c284c2c
[ EMERG] [ap] arm_registerdump: IP: 2c58ba4a SP: 3c4756e0 LR: 3c049ea4  PC: 00000000
[ EMERG] [ap] arm_registerdump: xPSR: 610f0000 BASEPRI: 000000e0 CONTROL: 00000004
[ EMERG] [ap] arm_registerdump: EXC_RETURN: ffffffa8
[ EMERG] [ap] arm_dump_stack: IRQ Stack:
[ EMERG] [ap] arm_dump_stack: sp:     3c41c900

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-28 22:52:28 +08:00
Jiuzhu Dong
b03f2e34b8 lseek: use type:off_t for return value
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-03-28 22:49:37 +08:00
Jiuzhu Dong
a8866132c2 ramlog: support setting threshold value of ramlog for poll waiters
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-03-28 22:48:56 +08:00
ligd
ed49aa1906 pm: remove unnecessary depends on OSINIT_OS_READY
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-03-28 22:48:14 +08:00
Ville Juven
43d5f60a74 MPFS: Fix issue with external interrupt detection
The bitmask overflow'd. Failing test is at mpfs_irq_dispatch / line 69
2022-03-28 22:40:11 +08:00
Ville Juven
30c25a95f3 MPFS: Fix error in flat build linker script
Use sram instead of ksram (copy&paste error)
2022-03-28 14:05:51 +03:00
zhuyanlin
c0c0ffdf2f xtensa: add xtensa_spill_window declaration
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-28 12:33:07 +02:00
yinshengkai
cdabac7ab1 nuttx/include: fix list.h type error
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2022-03-28 12:43:27 +03:00
Huang Qi
ad1098d413 arch/armv7-a: Fix a typo in Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 12:42:43 +03:00
Xiang Xiao
7b97b3ad70 input/touchscreen: Fix the typo error
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-28 12:33:48 +03:00
Xiang Xiao
3aaa7e8591 arch/sim: Remove "or 480" from Kconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-28 09:16:38 +03:00
Xiang Xiao
30e80f2394 arch/sim: Remove the unused SIM_TCNWAITERS from Kconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-03-28 09:16:38 +03:00
lishaoen
aa0c9fd788 nuttx: Add new config ARM_HAVE_MVE for MVE instruction
Signed-off-by: lishaoen <lishaoen@xiaomi.com>
2022-03-28 08:51:24 +03:00
Huang Qi
83a5e9958f arch/risc-v: Correct comments for current implementations
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-28 13:41:57 +08:00