Summary
Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
the change do this
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Sumary
add hostfs support for arm64, it's a copy
from arm32.
Note:
it's not support for opendir and readdir, command
like ls will not work.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
add set/get_power operation for sim_framebuffer to avoid assert
in fb_ioctl(cmd= FBIOSET_POWER/FBIOGET_POWER)
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
(IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
support mmio transport layer, and the new framwork support
more transport layer and this commit has implemented all the
old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
configs, and update its README.txt;
New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
| | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh | 539Mbps | 524Mbps | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp | 401Mbps | 437Mbps | 583Mbps | 505Mbps |
| rv-virt:netnsh | 487Mbps | 512Mbps | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp | 387Mbps | 455Mbps | 447Mbps | 502Mbps |
| rv-virt:netnsh64 | 602Mbps | 595Mbps | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp | 414Mbps | 515Mbps | 491Mbps | 525Mbps |
| rv-virt:knetnsh64 | 515Mbps | 457Mbps | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp | 308Mbps | 389Mbps | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
Tested in QEMU 7.2.2
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
The first time interrupt nesting occurs between REE and TEE,
CURRENT_REGS needs to be set.
If TEE nesting REE breaks, then EXC_RETURN.S=0,EXC_RETURN.ES=1;
Conversely, EXC_RETURN.S=1,EXC_RETURN.ES=0;
Interrupt nesting between TEE and REE can be determined based
on the S and ES bits of EXC_RETURN.
Only once nesting between TEE and REE is supported, and cyclic
nesting between TEE and REE is not supported.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack;
Signed-off-by: wangming9 <wangming9@xiaomi.com>
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack;
Signed-off-by: wangming9 <wangming9@xiaomi.com>
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack，add arm_initialize_stack;
Signed-off-by: wangming9 <wangming9@xiaomi.com>
VELAPLATFO-12536
This provides the initial hooks for Flattened Device Tree support
with QEMU RV. It also provides a new procfs file that exposes the
fdt to userspace much like the /sys/firmware/fdt endpoint in Linux.
See https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-firmware-ofw
Nodes in the fdt are not yet usable by the OS.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Signed-off-by: liaoao <liaoao@xiaomi.com>
For TEE & REE, securefault & busfault are not banked, so the faults can
only forword to TEE/REE.
But how to crash dump the other core which not handled faults ?
Here we provide a way to resolve this problem:
1. Set the securefault & busfault to TEE
2. busfault happend from TEE, then directly dump TEE
3. busfault happend from REE, then generate nonsecurefault
4. Back to REE, and dump
Signed-off-by: ligd <liguiding1@xiaomi.com>
We can use the driver in nuttx to download
files with debugger
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: chao an <anchao@xiaomi.com>
FlexCAN before used interrupts to process incoming frames.
This patch adds a HPWORK workqueue to process incoming frames in the workqueue
context instead. Also renamed mbi to txmb for better readability.
This PR adds support for the StarFive JH7110 RISC-V SoC. This will be used by the upcoming port of NuttX for PINE64 Star64 SBC. [The source files are explained in the articles here](https://github.com/lupyuen/nuttx-star64)
Modified Files in arch/risc-v:
Kconfig: Added ARCH_CHIP_JH7110 for JH7110 SoC
New Files in arch/risc-v:
include/jh7110/chip.h: JH7110 Definitions
include/jh7110/irq.h: Support 127 External Interrupts
src/jh7110/chip.h: Interrupt Stack Macro
src/jh7110/jh7110_allocateheap.c: Kernel Heap
src/jh7110/jh7110_head.S: Linux Header and Boot Code
src/jh7110/jh7110_irq.c: Configure Interrupts
src/jh7110/jh7110_irq_dispatch.c: Dispatch Interrupts
src/jh7110/jh7110_memorymap.h: Memory Map
src/jh7110/jh7110_mm_init.c, jh7110_mm_init.h: Memory Mgmt
src/jh7110/jh7110_pgalloc.c: Page Allocator
src/jh7110/jh7110_start.c: Startup Code
src/jh7110/jh7110_timerisr.c: Timer Interrupt
src/jh7110/hardware/jh7110_memorymap.h: PLIC Base Address
src/jh7110/hardware/jh7110_plic.h: PLIC Register Addresses
src/jh7110/Kconfig: JH7110 Config
src/jh7110/Make.defs: Makefile
* Error handling for abnormal interrupts and DMA errors is now
enabled for all builds, regardless of any DEBUG configuration.
* Error handling resets the MAC for the specific errors that
may halt the Ethernet operation, instead of everything as it
was before.
The window opens when the fb opens and closes when the fb closes.
test step: run fb demo, 1. ./nuttx 2. fb
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
- Added Wi-Fi related symbols to the kernel-space linker;
- Allocate more RAM to the kernel (to be useb by the Wi-Fi driver).
- Create a specific defconfig.
Instead of setting kernel/user space instruction and data ROM as
hard-coded values on linker, set them according to the max size
of the kernel image set by CONFIG_ESP32S3_KERNEL_IMAGE_SIZE. This
is done by making KIROM, UIROM, KDROM and UDROM dependent on the
kernel size value. Also, override CONFIG_NUTTX_USERSPACE config
according to CONFIG_ESP32S3_KERNEL_IMAGE_SIZE by using a custom
PREBUILD definition.
when executing ioctl AUDIOIOC_GETBUFFERINFO,the priv->pcm is still NULL,
so it will return -ENXIO,we can remove this check at the start of ioctl
and add in the case where it is used.
Signed-off-by: shipei <shipei@xiaomi.com>
When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
stack_t used by sigaltstack, make it compile sucess in sim.
Signed-off-by: yangyalei <yangyalei@xiaomi.com>
ltp: fix compile errors
Signed-off-by: yangyalei <yangyalei@xiaomi.com>
Instead of clearing the fields individually, just wipe the whole register.
This can be done because flags and rm are just parts of the fcsr.
31 8 5 0
+--------------+--------+-----------+
| | | |
| RESERVED | FRM | FSTATUS |
| | | |
+--------------+--------+-----------+
FCSR
- Save the FPU registers into the tcb so they don't get lost if the stack
frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
- Save ONLY if FPU is dirty
- Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.
Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
If the cache is already enabled before NuttX starts up,
enabling the cache in NuttX will cause the cache to be
re-invalidated, then resulting in data that is already
in the cache being flushed out.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Basically, it reserves an area of the RTC memory to preserve the
RTC timer.
Please refer to:
fa76c82a5b
This commit also removes the rtc.dummy section because C3, C6 and
H2 don't need to skip it once the region is accessed by the same
address space using the instruction and data bus.
1. add lib_fork api in libs/libc, we need a fork() api to implement the
fork relative method, such as pthread_atfork
2. rename the assembly fork entry function name to up_fork(), and rename
the up_fork() to arch specific name, such as
sim_fork()/arm_fork()/mips_fork() etc.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Clone the esp-hal-3rdparty repository and, then, checkout to a
specific version (usually indicated by the commit SHA) instead of
using a branch as the HEAD.
Also switch to automatic one by default, as it saves a lot of flash. The manual training
code is left in for now to be able to use it as an option if there are problems with automatic one
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The implementation of up_perf_*() is in a different static library in nuttx:
Hardware: libarch.a
Software: libdrivers.a (weak function)
Since functions with weak attributes cannot be correctly replaced in multiple static libraries,
this PR will use macros to replace whether the arch supports hardware perf events
Signed-off-by: chao an <anchao@xiaomi.com>
If -fstack-protector-all is enabled, gcc linker will need GCC
SSP(Stack Smashing Protector) support, Since the implement of SSP
is related to the OS, most of embedded toolchain does not provide
ssp support, so an error will be reported when linking:
enable CONFIG_LTO_FULL && CONFIG_STACK_CANARIES
arm-none-eabi/bin/ld: cannot find -lssp_nonshared: No such file or directory
arm-none-eabi/bin/ld: cannot find -lssp: No such file or directory
https://github.com/gcc-mirror/gcc/blob/master/gcc/gcc.cc#L983-L985
Since nuttx has already implemented SSP related hook functions,
so in this PR, we filter out this option in the link phase to ensure that
the implementation of lssp/lssp_nonshared will not be referenced
Signed-off-by: chao an <anchao@xiaomi.com>
Writes to MPFS_CFG_DDR_SGMII_PHY_EXPERT_DFI_STATUS_OVERRIDE register were not done properly. Use correct address for writes.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Reading the CSD field misses 3 bytes as the residual bytes
are not carried over properly. Fix this by adding the missing
bytes due to shifting.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
According to the ARMv7a/r/m and ARMv8m architecture manuals
The allowed values are
0 Data or unified cache.
1 Instruction cache.
"One CCSIDR is implemented for each cache that can be accessed by the processor. CSSELR selects which Cache Size ID Register is accessible, see c0, Cache Size Selection Register (CSSELR)."
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Remove TABs
Fix indentation
Fix Multi-line comments
Fix Comments to the Right of Statements.
Fix nuttx coding style
Fix Comments to the Right of Statements.
In the current implementation of other architectures, it is not really implemented to preserve the context, so it is emulated from other architectures to clear the context.
If this behavior is not implemented, it will cause the xtensa architecture processor to loop assert in the active assert case
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
1. as we can use fork to implement vfork, so we rename the vfork to
fork, and use the fork method as the base to implement vfork method
2. create the vfork function as a libc function based on fork
function
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Fix goldfish build toolchain math library error:
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:454:9: error: 'nexttowardf' has not been declared in '::'
454 | using ::nexttowardf;
| ^~~~~~~~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:472:9: error: 'acosl' has not been declared in '::'
472 | using ::acosl;
| ^~~~~
/mnt/yang/vela_Goldfish/nuttx/include/libcxx/cmath:473:9: error: 'asinl' has not been declared in '::'
473 | using ::asinl;
| ^~~~~
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
armv8-m/arm_securefault.c:69:3: warning: implicit declaration of function 'syslog_flush'; did you mean 'syslog_like'? [-Wimplicit-function-declaration]
1. Update all CMakeLists.txt to adapt to new layout
2. Fix cmake build break
3. Update all new file license
4. Fully compatible with current compilation environment(use configure.sh or cmake as you choose)
------------------
How to test
From within nuttx/. Configure:
cmake -B build -DBOARD_CONFIG=sim/nsh -GNinja
cmake -B build -DBOARD_CONFIG=sim:nsh -GNinja
cmake -B build -DBOARD_CONFIG=sabre-6quad/smp -GNinja
cmake -B build -DBOARD_CONFIG=lm3s6965-ek/qemu-flat -GNinja
(or full path in custom board) :
cmake -B build -DBOARD_CONFIG=$PWD/boards/sim/sim/sim/configs/nsh -GNinja
This uses ninja generator (install with sudo apt install ninja-build). To build:
$ cmake --build build
menuconfig:
$ cmake --build build -t menuconfig
--------------------------
2. cmake/build: reformat the cmake style by cmake-format
https://github.com/cheshirekow/cmake_format
$ pip install cmakelang
$ for i in `find -name CMakeLists.txt`;do cmake-format $i -o $i;done
$ for i in `find -name *\.cmake`;do cmake-format $i -o $i;done
Co-authored-by: Matias N <matias@protobits.dev>
Signed-off-by: chao an <anchao@xiaomi.com>
This small fix ensures all DMA pointers are correctly reseted during
DMA setup (when the driver is opened). Without this there could be rare
occurrence of driver pointer to incorrect (invalidate) DMA buffer and thus
saving incorrect characters to upper layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Circular buffer does not use DMA linked list therefore function
sam_freelinklist() cannot be called as it would fail on assertion (csa
not defined). Peripheral that calls DMA should care of buffer invalidation
instead.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Port based on arch/arm/nrf53.
Modem not fully supported yet. At the moment, initialization and AT interface work.
Sockets and GNSS interface will be added later.
Reference:https://xpack.github.io/blog/2022/05/18/riscv-none-elf-gcc-v12-1-0-2-released/
RISC-V ISA updates
Compared to previous releases, starting from 12.x, the compiler implements the new RISC-V ISA, which introduces an incompatibility issue, and builds might throw error messages like unrecognized opcode csrr.
The reason is that csr read/write (csrr*/csrw*) instructions and fence.i instruction were separated from the I extension, becoming two standalone extensions: Zicsr and Zifencei.
The solution is to add _zicsr and/or _zifencei to the -march option, e.g. -march=rv32imac becomes -march=rv32imac_zicsr_zifencei.
Initialize ICACHE way with correct mask.
Initialize scratchpad with constant g_init_marker as it has been done in HSS
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
Summary:
- I noticed that arm64_gic_raise_sgi() is not implemented for
GICv2 which is used for SMP + hypervisor such as qemu + kvm.
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I noticed that pcsi version can not be obtained with qemu + kvm.
- Also, pci_detect hangs with qemu + hvf.
- This commit fixes this issue by using hvc (hypervisor call).
Impact:
- None
Testing:
- Tested with qemu-7.1 + kvm (linux) and qemu-7.1 + hvf (macOS)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- During testing with qemu + kvm, I noticed that nuttx hangs
when setting cntfrq_el0. With qemu + kvm, it starts from
EL1 because we can not specify virtualization=on
- However, I noticed that it works without setting cntfrq_el0
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with qemu-7.1 (both with kvm and without kvm)
- NOTE: to work with kvm, GICv2 must be used.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
CONFIG_ARM_TOOLCHAIN_GNU_EABI build got broken when -mthumb option was moved
from ARCHCPUFLAGS to ARCHOPTIMIZATION variable:
arm-none-eabi-ld: error: .../build/nuttx/nuttx uses VFP register arguments, /usr/lib/gcc/arm-none-eabi/5.4.1/libgcc.a(_fixunsdfdi.o) does not
arm-none-eabi-ld: failed to merge target specific data of file /usr/lib/gcc/arm-none-eabi/5.4.1/libgcc.a(_fixunsdfdi.o)
arm-none-eabi-ld: error: .../build/nuttx/nuttx uses VFP register arguments, /usr/lib/gcc/arm-none-eabi/5.4.1/libgcc.a(_udivmoddi4.o) does not
arm-none-eabi-ld: failed to merge target specific data of file /usr/lib/gcc/arm-none-eabi/5.4.1/libgcc.a(_udivmoddi4.o)
Changes the executable type built against the `make export` target fully linked by default. This greatly improves performance when loading applications, as relocations no longer need to be processed.
This change allows boards to define an additional kconfig option, which specifies the final link format of application executables.
By selecting `CONFIG_BINFMT_ELF_RELOCATABLE`, and providing an appropriate linker script, applications can be fully linked, removing the need to process relocations.
In the default configuration, the Litex ethernet peripheral contains two RX and two TX buffers. The active buffer for the peripheral should be swapped as soon as possible, in order to reduce packet loss.
This modification acknowledges the receive buffer as soon as the pending data is copied into the NuttX device data buffer. Improving reliability under heavy load.
since symbols defined in arch/elf.h is also used in other case, for example:
CC: pthread/pthread_testcancel.c machine/arm/gnu_unwind_find_exidx.c:32:8: error: unknown type name '__EIT_entry'
32 | static __EIT_entry *__exidx_start_elf;
| ^~~~~~~~~~~
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The following macros
__ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_FLASH_H
__ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H
are used in other header files.
Signed-off-by: Mingjie Shen <shen497@purdue.edu>
When asserting, automatically analyze whether
there is a deadlock in the thread, and if there
is a deadlock, print out the deadlocked thread.
The principle is to analyze whether there is
a lock ring through the tcb holder.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
- Save the FPU registers into the tcb so they don't get lost if the stack
frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
- Save ONLY if FPU is dirty
- Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.
Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
This adds support for the CoreMMC v3.1 FPGA driver as described
in Microchip Handbook HB0510. The driver doesn't support DMA.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
USBD has many limitation that make it hard to work properly:
- only one EasyDMA channel which must be shared for all EPs
- only one DMA transfer can take place at a time
- some registers are unavailable during DMA transfer
- in case of any problems, the peripheral silently blocks,
or lose the transmitted bytes without information for the user
This commit is trying to fix these problem and makes the USBS stack more reliable.
Tested with high-speed CDCACM data transfers and that's the best I've been able to get in terms of stability.
if config_walltime_signal is enabled, NuttX_sim will receive a lot of
signals, the socket api will break and errno will be EINTR, masking irq
before calling the host socket api will avoid this problem.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
In SMP mode, the fpu owner may switch from core0 to core1,
so it is necessary to force saving the FPU context when a
context switch occurs.
This PR fixed the crash issue mentioned in #8799.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
If a kernel stack exists, use that whenever the user process is in
privileged mode, i.e. running an exception or in system call. Previously
the exception context was stored into the user's stack, which is not ideal.
Why?
1. Because the exception entry status (REG_INT_CTX) is needed by the
kernel, and this is now in user memory which requires that the correct
user mappings are active when it is accessed.
2. The user must currently account for the exception stack frame (which
is BIG) in its own stack allocation. Moving the exception context save
to the kernel stack offloads this responsibility from the user to the
kernel, which is IMO the correct behavior.
3. The kernel access to user memory is currently allowed without condition,
however this is not ideal either. The privileged mode status CSR allows
blocking access to user memory via the STATUS_SUM-bit, which should be
disabled by default and only enabled when access to user space is really
needed. This patch allows implementing such features.
This is preparation to use kernel stack for everything when the user
process enters the kernel. Now the user stack is in use when the user
process runs a system call, which might not be the safest option.
This is a minimalistic SBI implementation for NuttX.
Provides a single service for now:
- Access to machine timer
Provides a start trampoline to start NuttX in S-mode:
- Exceptions / faults are delegated to S-mode.
- External interrupts are delegated to S-mode.
Machine mode timer is used as follows:
- The timer compare match register reload happens in M-mode, via
call gate "riscv_sbi_set_timer"
- The compare match event is dispatched to S-mode ISR, which will
notify the kernel to advance time
- Clearing the STIP interrupt does not work from S-mode,
so the call gate does this from M-mode
The only supported (tested) target for now is MPFS.
CortexR52 can have a optional FPU.
- VFPv3 with FP16
- Option 1: 16 x double-prevision registers - -mfpu=vfpv3-d16-fp16
- Option 1: 32 x double-prevision registers - -mfpu=vfpv3-fp16
Summary:
- I noticed that ./tools/configure.sh fvp-armv8r:nsh_smp shows
warning: (ARCH_CHIP_FVP_R52 && ARCH_CHIP_FVP_R82) selects ARMV8R_HAVE_GICv3 which has unmet direct dependencies (ARCH_ARM && ARCH_ARMV8R)
- I think ARMV8R_HAVE_GICv3 is only used for aarch32.
- This commit fixes this issue.
Impact:
- None
Testing:
- Tested with nsh_smp on FVP
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This adds functionality to map pages dynamically into kernel virtual
memory. This allows implementing I/O remap for example, which is a useful
(future) feature.
Now, the first target is to support mapping user pages for the kernel.
Why? There are some userspace structures that might be needed when the
userspace process is not running. Semaphores are one such example. Signals
and the WDT timeout both need access to the user semaphore to work
properly. Even though for this only obtaining the kernel addressable
page pool virtual address is needed, for completeness a procedure is
provided to map several pages.
During initialization it isn't possible to use up_puts once it's
protected against concurrent access through a mutex lock. Instead,
using up_putc makes it similar to ESP32S2 and ESP32S3 and perfectly
fits for showprogress usage.
Basic work required for uniprocessor CortexR52 (ARMv8R AARCH32) using
GICv3 and CP15 mapped arch timer.
Tested on ARM FVP 11.20.
Port is based on ARMv8R AARCH64 and ARMv7R code. Excuse possible copy-paste leftovers.
Remove unnecessary reading of the status register when loading / unloading
the FIFOs. Reading from the IP block is slow due to BUS synchronization and
this basically makes the SPI busy loop for no reason at all, destroying the
CPU usage.
The overall benefit of these changes is approx. 25%-points, which is a
MASSIVE improvement.
Adds a driver for an FPGA fabric / CoreSPI implementation.
Supports multiple instances, assuming they reside in some base address,
offsettable by a constant value.
Add an interface that validate if EasyDMA transfer is possible.
EasyDMA cannot access flash memory which can cause hard to detect silent bugs.
This feature is enabled if CONFIG_DEBUG_FEATURES=y and CONFIG_DEBUG_ASSERTIONS=y.
External function to query vbus status. Reading from the block requires
the clock, but if no devices are open -> vbus detect does not work.
This creates a chicken / egg problem, if vbus detect is used to start
the usb device.
bmp388 works poorly as the system fires STOPs even in
a beginning of a transaction. Don't let unrelated STOPs
to distort the data flow.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This adds 2 more FPGA I2Cs. Also rework the indexing
so that it matches the earlier work without major changes.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This fixes the following issue:
- After sending the address, the driver writes an extra zero
Without this patch, the extra write causes an extra ACK that would
terminate the sequence prematurely. This is observed as data read
corruption.
With this fix, the condition is detected precisely. That being the
case, the sequence is continued with a repeated start, after which
the read continues normally.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This incorporates an fpga i2c driver into the existing i2c driver.
This fpga i2c works almost 100% as the MSS i2c, but the difference
is that the fpga driver terminates all transactions with a stop
sent -interrupt. That needs to be handled.
Fpga clock source is also different, act accordingly.
SEC2TICK(10) is an overkill to any app, use just one second instead.
modifyreg32s are simplified as well, no need to clear and set
as set is enough.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
I2C status register reset value (0xf8) was not handled properly causing unnecessary bus resets.
Added critical section to mpfs_i2c_reset() and removed unnecessary interrupt disabling elsewhere.
Confirmation of the IN request must be done immediately after all data has been transferred,
otherwise sending data when more than one request has been added to the queue will
not work properly.
- Update TrustedFirmare-M instructions to latest version of STM32CubeL5
- Increase idle thread stack size to not overflow during system init
- Select ARCH_HAVE_TRUSTZONE for STM32L5
- Set CONFIG_ARCH_TRUSTZONE_NONSECURE for stm32l562e-dk:nsh, since NuttX
is running in the Non-secure world.
See https://github.com/apache/nuttx/issues/9316
Signed-off-by: Michael Jung <michael.jung@secore.ly>
Whenever a SPI flash operation is going to take place, it's
necessary to disable both the instruction and data cache. In order
to avoid the other CPU (if SMP is enabled) to retrieve data from
the SPI flash, it needs to be paused until the current SPI flash
operation finishes. All the code that "pauses" the other CPU (in
fact, the CPU spins until `up_cpu_resume` is called) needs to run
from the instruction RAM.
SAMv7 QSPI peripheral does not copy-in/out directly into/from
user provided buffer, but use a dedicated memory that is interfaces
using byte copy. The QSPI command buffer can point to memory with
any alignment
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Add a new field to record the global on the basis of mm_backtrace.
When using alloc, the field is incremented by 1,
so that the memory usage can be dumped within the range
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
armv8r and armv8a have different process affinity,
and sgi affinity needs to be able to adapt all of them.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Summary
For ARM64, it need to set IRQ type(EDGE or LEVEL). it's specific
for ARM64 PPI or SPI.
The change add arm64_gic_irq_trigger to set IRQ type
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary
add up_affinity_irq/up_trigger_irq/up_prioritize_irq for gicv3
these interface is necessary for some drivers
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Summary:
GICR_PWRR is a IMPLEMENTATION-DEFINED register for gc700/gc600, which
is following gic v3 and v4.
Please check GICR_PWRR define at TRM of GIC600/GIC700 for more detail
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
The compiler will optimize boot_early_memset to memset,
but memset in libc cannot be used before MMU is enabled.
Therefore, assembly language is used to implement the
initialization of bss to avoid this problem.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
