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10751 Commits

Author SHA1 Message Date
Gregory Nutt
447785b264 SAMD/L21: Need to preserve errno value across syslog() call. 2017-07-12 16:22:23 -06:00
Gregory Nutt
10fbb2b089 SAMD/L21 USB: Remove all commented out logic. 2017-07-12 08:10:21 -06:00
Janne Rosberg
76ea6f09ec SAMD/L21: Add a USB driver. Developed for Filament Inc. by Offcode, LTD. 2017-07-12 07:46:46 -06:00
Matt Thompson
5448c99ff2 I was having issues with the bus freezing up .. slaves holding SDL low.. so I rewrote a good portion of the interrupt logic based on the application notes from Atmel. One major improvement is using the RXNACK flag in the STATUS register, which indicates that no device responded to an address packet. Assuming that the chip will always give an interrupt status, I believe it's possible to eliminate the timer as well. 2017-07-12 06:44:53 -06:00
Matt Thompson
1e0560b22f SAMD21: Fix some SPI-related issues. 2017-07-11 12:48:38 -06:00
Gregory Nutt
839019f305 SAMD/L21 I2C: Another update... needs to use enter/leave_critical_section vs. old irqsave/restore. 2017-07-11 07:01:05 -06:00
Alan Carvalho de Assis
5b9526b4c1 SAML21 I2C driver. Developed for and contributed with permissin from Filament company. 2017-07-11 06:58:58 -06:00
Gregory Nutt
79e5d2b7b6 STM32 TIM3/4 are always 16-bits; never 32-bits. Noted by Eetu Nevalainen. 2017-07-10 13:56:06 -06:00
Gregory Nutt
76587b2c6f STM32 Kconfig: 'unfold' some of the dependencies to provide better long term configuration support. This also effective reverts the recent 15b85738e7 2017-07-06 10:34:54 -06:00
Gregory Nutt
47be509d79 Rename CONFIG_STM32_STM32F40XX to CONFIG_STM32_STM32FXXXX since it is used by F4 parts other than F40x 2017-07-06 10:20:14 -06:00
gwenhael.goavec
15b85738e7 In arch/arm/src/stm32/Kconfig when the CPU is a STM32F4, some STM32_HAVE_xx with xx = {OTGFS, TIM3, TIM4, SPI3, I2S3, I2C3} are selected by default. But for F410 these peripherals are absent. This change add tests to check if the target CPU is an F410 or not and selects according to the situation. This also adds a select for STM32_HAVE_DAC1 present on this STM32 flavor. 2017-07-06 09:52:21 -06:00
Eetu Nevalainen
21dcc8cbc7 stm32f40xxx_rtcc ISR register and write protection fix 2017-07-03 11:06:07 -06:00
Gregory Nutt
68315b7444 Merged clang into master 2017-07-03 07:04:57 -06:00
Gregory Nutt
09ab651e02 samv71-xult: Add support for the MRF24J40 radio and create a mrf24j40-starhub configuration. A few fixes to IPv6 and 6LoWPAN were required to have 6LoWPAN and Ethernet coexisting. Untested and expect some complexity in the bring-up. 2017-07-02 11:04:57 -06:00
Gregory Nutt
cf44fd6ec0 Add CLANG definitions in Kconfig and Toolchain.defs 2017-07-02 06:42:48 -06:00
Gregory Nutt
1c5ec07414 arch/: Remove dangling space at the end of lines. 2017-06-28 13:16:48 -06:00
Gregory Nutt
aa1708e7c0 6LoWPAN: Update README; fix duplicate and bad memcpy in loopback driver. 2017-06-26 10:53:57 -06:00
raiden00pl
715d6fa9ff stm32f33xxx_rcc: cleanup + move hrtim clock source selection 2017-06-26 18:30:10 +02:00
raiden00pl
aead2b2afd stm32f33xxx_rcc.h: fix typo 2017-06-26 18:26:59 +02:00
Juha Niskanen
56eeb40958 STM32L4 serial: Allow configuring Rx DMA buffer size 2017-06-26 09:19:42 -06:00
Juha Niskanen
90ccdf287d STM32 L4 DMA: Correct USART3_RX bad channel definition 2017-06-21 08:40:33 -06:00
David Sidrane
345ea957cf Merged in david_s5/nuttx/upstream_kinetis (pull request #414) 
Kinetis:I2C fixed mis-placed kinetis_i2c_endwait

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-20 20:22:17 +00:00
David Sidrane
839a6e09f4 Kinetis:I2C fixed mis-placed kinetis_i2c_endwait 
Fixed accedently replaced post with wait.
 2017-06-20 10:01:35 -10:00
Gregory Nutt
5de74441a6 Costmetic change from review of last PR 2017-06-20 13:33:14 -06:00
David Sidrane
1ee03d7500 Merged in david_s5/nuttx/upstream_kinetis (pull request #413) 
Kinetis:I2C driver added I2C3, reference counting and reset

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-20 19:31:38 +00:00
David Sidrane
9e0f583774 Kinetis:I2C driver added I2C3, reference counting and reset 
Refactored the driver to support reference counting and reset
   added I2C3
 2017-06-20 08:34:12 -10:00
Sebastien Lorquet
0bf4893b2c STM32: Allow clock frequencies > 168 Mhz on stm32f427/429. We need to enable the power overdrive for this case. This patch allows the required bits to be set in proper sequence. It also modifies the local register access operations to allow more than 16-bit registers. 2017-06-20 11:56:54 -06:00
Juha Niskanen
326ab01a91 STM32 F7: Set I2C4 SDA and SCL pins to open drain mode 2017-06-20 08:06:30 -06:00
Juha Niskanen
2c548a4e58 STM32 L4: I2C4 was writing to wrong RCC registers 2017-06-20 08:04:09 -06:00
Gregory Nutt
47ad81b3e5 Trivial spelling fix 2017-06-20 08:02:42 -06:00
Pekka Ervasti
2eb782961f STM32 L4: Set I2C SDA and SCL pins to open drain mode. 2017-06-20 07:59:27 -06:00
Jussi Kivilinna
a1ee9547f3 stm32_adc: invalidate dma buffer before use. Missing invalidation caused old samples being fetched from cache. 2017-06-19 07:52:19 -06:00
raiden00pl
c29c4e2ec2 stm32_hrtim: remove unneeded definitions 2017-06-18 18:08:25 +02:00
raiden00pl
4e0f45f252 stm32_hrtim: fix initialization bug, minor changes 2017-06-18 18:06:37 +02:00
raiden00pl
cd30545cd9 stm32_hrtim: ADC triggering and DAC synch events 2017-06-18 15:26:39 +02:00
raiden00pl
96e639262a stm32_hrtim: add hrtim ops 2017-06-18 11:01:36 +02:00
raiden00pl
797e286cb0 stm32_hrtim: timers mode configuration 2017-06-18 09:28:05 +02:00
raiden00pl
dfeffefa69 stm32_hrtim: typo 2017-06-18 08:02:15 +02:00
Gregory Nutt
0024840f7d Trivial, cosmetic changes from review of last PR 2017-06-17 14:44:11 -06:00
raiden00pl
b48a86ee33 Merge remote-tracking branch 'upstream/master' 2017-06-17 22:18:03 +02:00
raiden00pl
4d9d3c4a9c stm32_hrtim: cosmetics 2017-06-17 22:12:56 +02:00
raiden00pl
5e3360b8b9 stm32_hrtim: faults and events configuration 2017-06-17 21:56:11 +02:00
David Sidrane
c79d4d1988 stm32:flash add CONFIG_STM32_STM32F469 to list defining OPTCR1 2017-06-16 14:16:32 -10:00
Gregory Nutt
5245cbc6f5 STM32 SPI/I2S: Back out a bad pin mapping change from 4ab2a3661e. Try to staighten out some I2C3 and SPI3 pin configuration stuff. 2017-06-16 09:34:22 -06:00
Sebastien Lorquet
4d9be9bc20 STM32 F4 FLASH: Enable/disable the flash write protection on any sector. I have verified it to work on the stm32f427. 2017-06-16 08:46:57 -06:00
raiden00pl
bd7bee5db0 stm32_hrtim: structures for deadtime and chopper, cosmetics 2017-06-16 11:36:23 +02:00
David Sidrane
64e3dc5e8b Merged in david_s5/nuttx/upstream_samv7_twi (pull request #399) 
samv7:twihs driver add reference counting

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-15 21:45:07 +00:00
David Sidrane
d9d32ac808 samv7:twihs driver add reference counting 2017-06-15 11:16:28 -10:00
raiden00pl
268c6d0b7d stm32_hrtim: outputs enable, period and compare functions, cosmetics 2017-06-15 16:45:21 +02:00
Gregory Nutt
d958cec7a4 Cosmetic changes from review of last PR 2017-06-15 06:58:55 -06:00
Hidetaka
0f1d388248 Merged in TJ-Hidetaka-Takano/nuttx-pr/feature/fix-kconfig (pull request #394) 
Fixed typo "CORTEXR5F" in arch/arm/Kconfig

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-15 12:12:31 +00:00
Hidetaka
9dfa8f7df9 Merged in TJ-Hidetaka-Takano/nuttx-pr/feature/fix-armv7m-toolchain-def (pull request #395) 
Fixed ARMv7-M Toolchain definition for Cortex-M4.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-06-15 12:12:01 +00:00
Hidetaka Takano
5591fc6b16 Fixed ARMv7-M Toolchain setting. 
- Cortex-M4 only have Single Precision FPU.
 2017-06-15 20:52:37 +09:00
Hidetaka Takano
d665392873 Fixed typo "CORTEXR5F" in arch/arm/Kconfig 2017-06-15 20:44:06 +09:00
raiden00pl
96d40dec40 stm32_hrtim: cosmetic 2017-06-15 11:20:40 +02:00
Leif Jakob
4a79547fb8 multiple fixes for stm32f1xx RTC clock 
- compile issues because of missing RTC_MAGIC #defines
- missing functionality based on RTC_MAGIC in RTC based on stm32_rtcounter.c
- IRQ setup from up_rtc_initialize was later reset in up_irqinitialize
- write access to backup registers without enabling access to backup domain
- possible races in set/cancel alarm
tested with STM32F103C8 only
device now wakes up from forced STANDBY mode by alarm
 2017-06-14 22:36:40 +02:00
David Sidrane
b2d929e40a Kinetis:SPI driver 2017-06-13 17:46:57 -10:00
David Sidrane
de3695d32b kinetis:lpserial fixed header inclusion 2017-06-13 17:46:56 -10:00
Gregory Nutt
e379491d13 STM32/STM32L4: Review of last commit -- Eliminate possible underflow 2017-06-13 07:05:46 -06:00
JM
7903a8a46c stm32/stm32l4 PWM: While attempting to output a 70 MHz square wave from the timer output of a STM32 clocked at 140 MHz (which works fine in baremetal C), I stumbled on what I believe to be an error in arch/arm/src/stm32/stm32_pwm.c. Line 1304 we are told that 
reload = timclk / info->frequency;

which I belive to be incorrect, it should be

reload = timclk / info->frequency - 1;

since starting to count from 0, if I want to output half of the TIM clock, I must count to 1 and not to 2.

Surely enough, the original code did output 140/3=47 MHz, while this correction does allow the output up to 70 MHz.

I am not sure this affects most users generating slow PWM (e.g. PX4) but for frequencies
close to the PCLK, indeed the difference becomes significant.
 2017-06-13 06:01:13 -06:00
raiden00pl
f6ba4642a3 stm32_hrtim: GPIOs configuration + EEV and FAULT strucutres 2017-06-12 18:45:58 +02:00
Gregory Nutt
f5f1c73b54 Based on the last PR, review all serial driver vector attachment. Found one additional error and updated all relevant drivers to current interrupt parameter passing. 2017-06-12 06:22:35 -06:00
Masayuki Ishikawa
93a2d52b56 i.MX6: Fix a wrong parameter passed when calling irq_attach() in imx_serial.c 2017-06-12 13:34:53 +09:00
raiden00pl
de8cd6c870 stm32_hrtim: add character driver 2017-06-11 20:51:23 +02:00
Gregory Nutt
fe813545e8 STM32F33: Forgot to add new files that were a part of the last patch before committing. 2017-06-11 11:00:29 -06:00
Mateusz Szafoni
437ad3ccb2 STM32F33: Fix hrtim definitions, Add beginning of HRTIM driver 2017-06-11 10:49:20 -06:00
Gregory Nutt
1e5125c5d5 STM32L4: Remove some C++ style comments. 2017-06-08 13:43:47 -06:00
Gregory Nutt
8b907c4c1f STM32L4: Fix a typo 2017-06-08 11:07:20 -06:00
Gregory Nutt
d99ceec58c STM32L4: Add STM32L475 pinmap. Initial cut is just the the L476 pinmap with unsupported devices removed. 2017-06-08 10:55:27 -06:00
Gregory Nutt
596fe68854 STM32L4: Add STM32L475 OTGFS header file. Not fully reviewed. 2017-06-08 10:34:26 -06:00
Gregory Nutt
95fcdff1fd STM32L4: Add STM32L475 RCC definitions/logic. 2017-06-08 10:04:28 -06:00
Gregory Nutt
1a405d2881 STM32L4: Add L475 syscfg register definitions. 2017-06-08 09:07:04 -06:00
Gregory Nutt
66e2247f30 STM32L4: Ad support for the STM32L475 family. Incomplete -- still needs pinmap, rcc, otgfs, syscfg 2017-06-08 08:52:09 -06:00
David Sidrane
4854eb1fd7 Kinetis:Fixed waning for kinetis_mpudisable 
Missing header file added
 2017-06-06 15:18:01 -10:00
David Sidrane
36da2b91c5 Kinetis:USB-FS driver 
Removed the notion of attached. The khci_usbattach is call early in
   the init either in board_initalize or in board_app_initalize. In
   either case it is always done prior to the the class register.
   Therefore the khci_usbattach call only set a flag, and that
   flag is only tested in the class register. The class register will
   enable the soft connect pull up.
 2017-06-06 14:39:00 -10:00
David Sidrane
cb62675b5e Kinetis:sim ensure isolation of clock dividers for 0 value case 
This fixes a bug were a SoC does not have a clockdivN register
   and passes a 0 for the init value. This prevents overflow of
   the 0 decremented to -1 (0xffffffff) spilling over to other
   clockdivN feilds.
 2017-06-06 14:38:59 -10:00
David Sidrane
60c552ae0f Kinetis:usbdev clean up ensuring proper use of HW. 
Remove magic numbers from code, documented the use of
  undocumented bits.

  Remove comments and code that were not appropriate for this
  hardware.

  Removed ifdef that's that were always compiled and removed code
  blocks that were never compiled.

  Ensure proper access order to hardware.
  Per the reference manual: disable endpoints prior to configuring buffer
  descriptor, then enable endpoints
  Reorganize interrupt processing order to offload data after processing
  errors.

  Reorganize initialization so that there is a clear initialization phase,
  reset phase for both the hardware and software structures.

  By breaking the initialization into smaller pieces, the reset interrupt
  only resets the resources within the controller that should be reset.

  Rework suspend and resume logic so they perform properly

  Made attach and detach functions optional. As they do not make sense for
  a bus powered device.

  Ensured the calls to up_usbinitalize up_usbuninitalize do not violate the
  USB spec.
 2017-06-06 14:38:59 -10:00
David Sidrane
c1a3208f83 Kinetis:Disable MPU when not in protected mode. 
The hardware reset state of the the MPU precludes any bus
   masters other then DMA access to memory. Unfortunately
   USB and SDHC have there own DMA and will not have access to
   memory in the default reset state.

   This change disabled the MPU if present on system startup.
 2017-06-06 14:38:58 -10:00
Gregory Nutt
4d46979a6f Tiva SSI: Resolves issue 52 'Copy-Paste error in tiva_ssibus_initialize()' submitted by Aleksandr Kazantsev. 2017-06-01 06:38:47 -06:00
Juha Niskanen
ad6515563b STM32L4 RTC: store RTC MAGIC to backup reg, not to address zero 2017-06-01 06:15:28 -06:00
Jussi Kivilinna
369b72f65a stm32f7: Add SPI DMA support 2017-05-31 09:13:20 -06:00
Juha Niskanen
14c233a2f5 STM32L4: gpio: put back EXTI line source selection 2017-05-31 06:34:14 -06:00
David Sidrane
a077d0285b Kinetis:Added ADC channel macro 2017-05-25 16:52:08 -10:00
David Sidrane
b407020968 Kinetis:Fixed typo in kinetis_adc.h 2017-05-25 16:51:25 -10:00
David Sidrane
488f42588b Kinetis:Removed base address from kinetis_adc.h 2017-05-25 16:50:42 -10:00
Juha Niskanen
0c9abbfe67 STM32L4: Add IWDG peripheral. This is the same as for STM32 except that prescale and reload can be 
changed after watchdog has been started, as this seems to work on L4.
 2017-05-23 07:02:36 -06:00
Gregory Nutt
32eb5ca99a Missed one change in the previous commit. 2017-05-21 15:02:00 -06:00
Gregory Nutt
7ffbb704d6 This is based on a patch by Taras Drozdovsky. Basically, the delay that was added during the integration of the CDC/ACM host driver was interfering with streaming audio. That delay was put there to prevent build endpoints from hogging the system bandwidth. So what do we do? Do we hog the bandwidth or do we insert arbitrarity delays. I think both ideas such. 2017-05-21 14:28:29 -06:00
Taras Drozdovsky
4ab2a3661e STM32F4: add cs43l22 audio driver and i2s driver 2017-05-21 14:14:09 -06:00
Juha Niskanen
819a6e049e stm32_i2c: make private symbols static 2017-05-19 07:16:01 -06:00
Gregory Nutt
989195cec8 STM32 Ethernet: Last patch breaks every board that does not use the KSZ80801 PHY. 2017-05-17 15:36:57 -06:00
Gregory Nutt
aac3a3df8e STM32 Ethernet: Should not stm32_phyintenable() return a failure if it could not enable the PHY interrupt? 2017-05-17 10:07:09 -06:00
Sebastien Lorquet
2c6ea23aee STM32 Ethernet: Add support for KSZ8081 PHY interrupts. 2017-05-17 10:04:49 -06:00
Juha Niskanen
8896f91f53 STM32L4: remove duplicate USART selects from Kconfig 2017-05-17 08:05:24 -06:00
Jussi Kivilinna
9169ff6a15 stm32_serial: fix freezing serial port. Serial interrupt enable/disable functions do not disable interrupts and can freeze device when serial interrupt is received while execution is at those functions. 
Trivially triggered with two or more threads write to regular syslog stream and to emergency stream. In this case, freeze happens because of mismatch of priv->ie (TXEIE == 0) and actually enabled interrupts in USART registers (TXEIE == 1), which leads to unhandled TXE interrupt
and causes interrupt storm for USART.
 2017-05-17 06:50:46 -06:00
Lederhilger Martin
b8e7d5c455 I had the problem that the transmit FIFO size (= actual elements in FIFO) was slowly increasing over time, and was full after a few hours. 
The reason was that the code hit the line "canerr("ERROR: No available mailbox\n");" in stm32_cansend, so can_xmit thinks it has sent the packet to the hardware, but actually has not. Therefore the transmit interrupt never happens which would call can_txdone, and so the size of the FIFO size does not decrease.

The reason why the code actually hit the mentioned line above, is because stm32can_txready uses a different (incomplete) condition than stm32can_send to determine if the mailbox can be used for sending, and thus can_xmit forwards the packet to stm32can_send. stm32can_txready considered mailboxes OK for sending if the mailbox was empty, but did not consider that mailboxes may not yet be used if the request completed bit is set - stm32can_txinterrupt has to process these mailboxes first.

Note that I have also modified stm32can_txinterrupt - I removed the if condition, because the CAN controller retries to send the packet until it succeeds. Also if the condition would not evaluate to true, can_txdone would not be called and the FIFO size would not decrease also.
 2017-05-16 07:47:18 -06:00
Gregory Nutt
b0fda33e13 Kconfig: Rename CONFIG_ARM_TOOLCHAIN_IAR to CONFIG_ARCH_TOOLCHAIN_IAR 2017-05-13 16:01:38 -06:00
Gregory Nutt
27805315f4 Tiva I2C: Correct an in conditional compilation 2017-05-13 14:01:42 -06:00
Gregory Nutt
6e4918c557 Remove CONFIG_ARM_TOOLCHAIN_GNU; replace with CONFIG_ARCH_TOOLCHAIN_GNU 2017-05-13 13:28:15 -06:00
Gregory Nutt
7fe112fe4c Kconfig/deconfigs: Add CONFIG_ARCH_TOOLCHAIN_GNU to indicate that the toolchain is based on GNU gcc/as/ld. This is in addition to the CPU-specific versions of the same definition. 2017-05-13 11:44:12 -06:00
Gwenhael Goavec-Merou
02535be36a STM32F410. Add support for STM32Fr10. STM32F410 is a version of STM32F4 with 32 KB of RAM and 62 or 128 KB of flash. 2017-05-13 08:40:09 -06:00
David Sidrane
c4a2e1399b Merged in david_s5/nuttx/upstream_kinetis (pull request #368) 
kinetis:K66 GPIO and pin mux cleanup

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-05-13 10:37:20 +00:00
David Sidrane
69a8aecbc8 kinetis:K66 define ALT1 to match ref manual 2017-05-12 17:21:54 -10:00
David Sidrane
700e4ff5b6 kinetis:K66 fixed TMP2_CH1 definition 2017-05-12 17:03:27 -10:00
Alan Carvalho de Assis
853d332b6c Move CAN subsystem to its own directory and put device drivers there 
Signed-off-by: Alan Carvalho de Assis <acassis@gmail.com>
 2017-05-12 11:48:47 -03:00
Juha Niskanen
46851b33b2 STM32L4: port stm32l4_serial_get_uart function from STM32F7 2017-05-12 15:54:48 +03:00
Gregory Nutt
0de294a586 Fix lots of occurrences of 'the the', 'the there', 'the these', 'the then', 'the they. 2017-05-11 13:35:56 -06:00
Gregory Nutt
3091050963 STM32L4: Review of last PR + Move separate stm32l4_flash.h; move hardware-specific definitions to chip/stm32l4_flash.h 2017-05-11 06:58:39 -06:00
Juha Niskanen
c74a51f789 STM32L4: add internal flash write support 2017-05-11 14:35:27 +03:00
Juha Niskanen
4f18b40429 mtd/config: erase block between block read and write 2017-05-10 08:25:39 -06:00
Juha Niskanen
e04ea9e3e3 Merged in juniskane/nuttx_stm32l4/stm32l4_dbgmcu_pr (pull request #361) 
STM32L4: add dbgmcu header files

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-05-09 17:06:32 +00:00
Gregory Nutt
3d73a04259 Merged l432kc into master 2017-05-09 11:03:42 -06:00
Gregory Nutt
2043e1a114 IOBs: Move from driver/iob to a better location in mm/iob 2017-05-09 07:35:30 -06:00
Juha Niskanen
ce1ad33289 STM32L4: add dbgmcu header files 2017-05-09 14:13:51 +03:00
Sebastien Lorquet
d591d3ac4e Restore settings for UARTs 4 and 5 2017-05-09 11:38:14 +02:00
Sebastien Lorquet
5204f19e4f fix typo found by Juha during review 2017-05-09 11:32:16 +02:00
Sebastien Lorquet
c1cf1269c7 Adapt stm32l43x pin definitions 2017-05-09 10:58:04 +02:00
David Sidrane
014b69e120 removed stray paren. 2017-05-08 22:56:05 +00:00
David Sidrane
8406b40baa Merged in david_s5/nuttx-16/david_s5/stm32serial-dma-buffer-round-off-not-up-1494258804216 (pull request #357) 
stm32:Serial DMA buffer round off not up

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-05-08 20:32:44 +00:00
Gregory Nutt
aa11d637a8 STM32 TIM: Add method to get timer width. Freerun timer: Use timer width to get the correct clock rollover point. 2017-05-08 12:33:15 -06:00
David Sidrane
546e7acb99 stm32:Serial DMA buffer round off not up 2017-05-08 15:54:03 +00:00
David Sidrane
b8ef079951 stm32:stm32_serial Forgot the -1 on mask 2017-05-08 03:43:36 +00:00
David Sidrane
0b2fb5a396 Merged in david_s5/nuttx/upstream_stm_dma (pull request #355) 
stm32: serial Allow configuring Rx DMA buffer size

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-05-06 17:49:48 +00:00
David Sidrane
b62ef579c8 stm32: serial Allow configuring Rx DMA buffer size 2017-05-06 05:16:21 -10:00
David Sidrane
5d6da5f4bb kinetis:Add ARCH_HAVE_I2CRESET 2017-05-06 04:52:48 -10:00
David Sidrane
97260321f2 kinetis:k66 Pin mux configure all I2C signals as Open Drain 
The output structure of the GPIO for I2C needs to be open
   drain.  When left at the default, one can observe on a scope
   the slave contending with the push-pull during the ACK
 2017-05-05 15:06:32 -10:00
David Sidrane
ce98cedb17 kinetis:k64 Pin mux configure all I2C signals as Open Drain 
The output structure of the GPIO for I2C needs to be open
   drain.  When left at the default, one can observe on a scope
   the slave contending with the push-pull during the ACK
 2017-05-05 15:06:24 -10:00
David Sidrane
af1f48c1c5 kinetis:k60 Pin mux configure all I2C signals as Open Drain 
The output structure of the GPIO for I2C needs to be open
   drain.  When left at the default, one can observe on a scope
   the slave contending with the push-pull during the ACK
 2017-05-05 15:06:14 -10:00
David Sidrane
1d9d13c426 kinetis:k40 Pin mux configure all I2C signals as Open Drain 
The output structure of the GPIO for I2C needs to be open
   drain.  When left at the default, one can observe on a scope
   the slave contending with the push-pull during the ACK
 2017-05-05 15:06:09 -10:00
David Sidrane
979e671cf0 kinetis:k20 Pin mux configure all I2C signals as Open Drain 
The output structure of the GPIO for I2C needs to be open
   drain.  When left at the default, one can observe on a scope
   the slave contending with the push-pull during the ACK
 2017-05-05 15:06:00 -10:00
Gregory Nutt
1cd3b3f590 Fix errors introduced into Kinetis serial when I unsuccessfully tried to correct coding standard violations. Folks, things will be better for everyone if you just follow that standard. 2017-05-05 14:47:11 -06:00
Gregory Nutt
0e49db7626 Add a blank line. 2017-05-05 09:35:47 -06:00
Juha Niskanen
35883ff9ae Merged in juniskane/nuttx_stm32l4/l4dev (pull request #347) 
STM32L4: add support for many new MCUs from STM32L4X3XX product line and Nucleo-L452 board

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-05-05 15:31:07 +00:00
David Sidrane
f29981e473 kinetis:Added HW flow control and termios 2017-05-05 07:33:15 -06:00
David Sidrane
b6a8db1b39 Kinetis: Use optional BOARD_OSC_CR and BOARD_OSC_DIV in clock configuration 2017-05-05 07:18:39 -06:00
David Sidrane
29ef635e89 Kinetis:Add OSC_DIV to the kinetis_osc header 2017-05-05 07:16:11 -06:00
David Sidrane
f73e2aab8d Kinetis:Fixed CLKSRC Bit Names 2017-05-05 07:14:00 -06:00
David Sidrane
2171523f50 Kinetis:Add TPM to K66 chip 2017-05-05 07:12:52 -06:00
Juha Niskanen
71accfc57b STM32L4: add more chips to Kconfig 
(This also removes DPFPU/DTCM/ITCM features again, fixing a
recent git history hickup.)
 2017-05-05 11:03:49 +03:00
Juha Niskanen
a5e9724224 STM32L4: firewall for stm32l4x3xx 
Not tested for any product family, but now it at least compiles.
L496 devices can have one bit wider Volatile Data Segment.
 2017-05-05 10:15:09 +03:00
Juha Niskanen
075a8b913c STM32L4: separate SYSCFG into product line specific files for clarity 2017-05-05 10:10:37 +03:00
Juha Niskanen
92f4277b1e Merged in juniskane/nuttx_stm32l4/stm32l4_i2c_pr (pull request #346) 
STM32L4: stm32l4_i2c: change wrong macro to CONFIG_I2C_POLLED

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-05-04 19:29:08 +00:00
Jussi Kivilinna
7035723aeb STM32F7 serial: Allow configuring Rx DMA buffer size 2017-05-04 07:09:19 -06:00
Jussi Kivilinna
acf0d17e5a Fix STM32F7 I2C interrupt handler 2017-05-04 06:51:44 -06:00
Juha Niskanen
80c2d384bb STM32L4: flash: update override config macros and add FLASH_CONFIG_B 2017-05-04 15:24:16 +03:00
Juha Niskanen
ae22eb224a STM32L4: changes needed for STM32L452 and Nucleo-L452RE board 
GPIO and UART seem similar across STMicro product matrix,
so renamed files accordingly. RCC is cloned just in case,
while conflicting differences there seem to be very minor.
 2017-05-04 15:23:38 +03:00
Juha Niskanen
dd1b9dfa81 STM32L4: modularize Kconfig to support different product lines/families 
This is modeled after STM32F7. Idea is to declare each chip in Kconfig
but allow for flash size override. Commit adds many STM32L4_HAVE_XXX
feature test macros.
 2017-05-04 15:22:51 +03:00
Juha Niskanen
c67c4a75ba STM32L4: stm32l4_i2c: change wrong macro to CONFIG_I2C_POLLED 2017-05-04 09:31:12 +03:00
Gregory Nutt
b0e880b04c Revert "STM32 I2C: More backward tests of CONFIG_I2C_POLLED. Needs to be reviewed." 
This reverts commit 1e054a2d3b.
 2017-05-03 18:26:24 -06:00
Gregory Nutt
11c14470c3 Merge remote-tracking branch 'origin/master' into photon 2017-05-03 17:36:52 -06:00
Gregory Nutt
1e054a2d3b STM32 I2C: More backward tests of CONFIG_I2C_POLLED. Needs to be reviewed. 2017-05-03 17:33:35 -06:00
David Sidrane
9b5ac56409 Fixed typo and backward ifdef 2017-05-03 23:10:48 +00:00
Juha Niskanen
ad3b941c44 STM32L4: stm32l4x6xx_pinmap: update I2C4 and DCMI pins 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-05-02 10:16:34 -06:00
Juha Niskanen
74e016d013 STM32F7: flash: macro naming errors, there is no FLASH_CONFIG_F for F7 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-05-02 10:14:46 -06:00
Gregory Nutt
e94865a317 Merge remote-tracking branch 'origin/master' into photon 2017-05-02 08:49:19 -06:00
Gregory Nutt
40b5c46024 STM32L4: Delete more references to DFPU, ITCM, and DTCM. 2017-05-02 08:03:21 -06:00
Mateusz Szafoni
1feaae7222 Merged in raiden00/nuttx (pull request #338) 
OPAMP support for STM32F33XX
 2017-05-02 13:57:56 +00:00
Juha Niskanen
a59b7bc932 STM32L4: add GPIO_PORTI definition 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-05-02 07:41:14 -06:00
Juha Niskanen
0eb14e9baa STM32L4: don't think these chips have DPFPU, DTCM or ITCM 2017-05-02 07:36:11 -06:00
Gregory Nutt
f7a28c09b0 Merge remote-tracking branch 'origin/master' into photon 2017-05-01 18:06:23 -06:00
Gregory Nutt
c59a5efcae STM32F0: I2C frequency quantization. Add logic to get closer if an oddball frequency is used. 2017-05-01 17:52:51 -06:00
Alan Carvalho de Assis
ccfdef6ddf STM32F0: Fix I2C frequency table 2017-05-01 17:41:57 -06:00
Gregory Nutt
e43b86dbd0 Merge remote-tracking branch 'origin/master' into photon 2017-04-30 17:42:37 -06:00
Gregory Nutt
a8ce97715b Tiva I2C: Update to use the standard parameter passing to interrupt handlers. 2017-04-30 14:44:39 -06:00
Gregory Nutt
0597eb5587 Fix a typo introduced in last commit. 2017-04-30 12:41:19 -06:00
Gregory Nutt
c172d7cf63 EFM32, STM32, and STM32 F7 I2C: Update to use the standard parameter passing to interrupt handlers. 2017-04-30 11:56:06 -06:00
Gregory Nutt
dee736bd0d STM32F0 I2C: Pin definitions should specify open drain (and probably 50Mhz). 2017-04-30 10:28:16 -06:00
Gregory Nutt
0a9dd3876b STM32F0 I2C: Upate driver to use the standard interrupt parameter passing logic. 2017-04-30 09:19:51 -06:00
raiden00pl
e4d47d61cc STM32F33: Add OPAMP support 2017-04-30 11:05:34 +02:00
Alan Carvalho de Assis
b688d41516 STM32F0 I2C: Initial cut at driver. Still a work in progress. 2017-04-29 16:53:47 -06:00
Gregory Nutt
f0bbe56620 STM32F0: Add some protection. There is only one interrupt for USART3-8. Current interrupt handling logic will support only one interrupt in that range. 2017-04-29 12:58:06 -06:00
Gregory Nutt
a7901f5c4c Merge remote-tracking branch 'origin/master' into photon 2017-04-29 12:35:01 -06:00
Gregory Nutt
e9a5477506 Add an instance argument to the SPIDEV definitions. 2017-04-29 12:26:52 -06:00
Gregory Nutt
f175af3cd3 More missed enum spi_dev_e forward references. 2017-04-29 08:29:01 -06:00
Gregory Nutt
b6b16bf4da Fix forward references that were mangled in last large changes. 2017-04-29 06:59:35 -06:00
Sebastien Lorquet
c56c6f7ccc ARM arch changes 2017-04-28 18:23:29 +02:00
Gregory Nutt
9431fb1d91 STM32L4: I2C was not using current interrupt handling parameter passing logic. 2017-04-28 08:21:02 -06:00
Juha Niskanen
b4d2651ca9 STM32L4: stm32l4_i2c: add I2C4 code 2017-04-28 08:09:16 -06:00
Gregory Nutt
2e6908b384 IOCTLS. Separate wireless character driver IOCTL commands from wireless network driver IOCTL commands. Move from wireless.h to ioctl.h. 2017-04-27 16:58:30 -06:00
Gregory Nutt
b608afc484 STM32F0: Fix some missing settings in the clock configuration logic 2017-04-27 15:44:05 -06:00
Gregory Nutt
92d761dfe3 STM32F0 Serial: Costmetic changes to spacing. 2017-04-27 09:15:18 -06:00
Sebastien Lorquet
c3119f06a2 Update STM32L4 README.txt file. 2017-04-27 08:37:14 -06:00
Juha Niskanen
f1b71e3ae7 TM32L4: Add some defines for the new peripherals in STM32L496 parts 2017-04-27 07:26:32 -06:00
Juha Niskanen
8a6662c957 TM32L4: Add some defines for the new peripherals in STM32L496 parts 2017-04-27 07:25:20 -06:00
Juha Niskanen
707d1e67fc STM32, STM32F7, STM32L4: Remove incorrect comment about STM32L1 LSE/RTC/LCD 2017-04-27 07:18:36 -06:00
Gregory Nutt
7d8140708e Merge remote-tracking branch 'origin/master' into photon 2017-04-26 10:42:19 -06:00
Simon Piriou
6bb2db8c15 bcmf: enable DMA for SDIO transfers 2017-04-26 17:23:53 +02:00
Gregory Nutt
232fbf7f00 CONFIG_DEBUG_HARDFAULT should be available for Cortex-M0 too. configs/nucle-f072rb/nsh: Correct amount of available SRAM in defconfig. 2017-04-26 07:45:40 -06:00
Juha Niskanen
06e4c4aedd STM32L4: add support for the STM32L496XX family 2017-04-25 08:47:50 -06:00
Simon Piriou
3bf5044306 stm32: cleanup stm32_sdio.c 2017-04-24 20:01:41 +02:00
Gregory Nutt
62966d915c Merge remote-tracking branch 'origin/master' into photon 2017-04-23 10:16:54 -06:00
Gregory Nutt
ca7d88f6bb SAM3/4: Fix a few more naming differences noted by Alan Carvalho de Assiss. 2017-04-23 08:14:49 -06:00
kc_dtm
db9143b2bd SAM3/4: Remove inappropriate semicolon. 2017-04-23 07:21:44 -06:00
Gregory Nutt
eb1d4ca774 SAM3/4: Fixed configurations for TWI master. Obviously an incomplete port from SAMA5. 2017-04-23 07:17:55 -06:00
Gregory Nutt
a55e937643 Correct mispelling 2017-04-22 17:03:34 -06:00
Gregory Nutt
79256573e1 net: network drver now retains Ethernet MAC address in a union so that other link layer addresses may be used in a MULTILINK environment. 2017-04-22 11:10:30 -06:00
Gregory Nutt
d8e4cbcfd5 Merge remote-tracking branch 'spiriou/wlan_dev' into photon 2017-04-22 08:26:40 -06:00
Jussi Kivilinna
325ba1a803 clock: add clock_resynchronize and use subseconds RTC 
Add clock_resynchronize for better synchronization of CLOCK_REALTIME and CLOCK_MONOTONIC to match RTC after resume from low-power state.

Add up_rtc_getdatetime_with_subseconds under CONFIG_ARCH_HAVE_RTC_SUBSECONDS to allow initializing (and resynchronizing) system clock with subseconds accuracy RTC.
 2017-04-21 08:45:57 -06:00
Juha Niskanen (Haltian)
c04c49dac0 Add support for the STM32F09X family. 2017-04-21 08:23:25 -06:00
Gregory Nutt
f902b8b058 Merge branch 'iob' 2017-04-20 16:09:14 -06:00
Gregory Nutt
bfb93338f6 Move net/iob to drivers/iob so that the I/O buffering feature can be available to other drivers when networking is disabled. 2017-04-20 16:08:49 -06:00
Gregory Nutt
73c7f05a3c Cosmetic changes to spacing and comments. 2017-04-20 14:08:08 -06:00
Gregory Nutt
d0ec395c42 Correct some spacing and some unused definition in some irq.h header files. 2017-04-20 12:39:21 -06:00
Gregory Nutt
bb54449889 STM32F0: Add an untested port of the F1 USB device to the STM32F0 2017-04-20 11:50:58 -06:00
Gregory Nutt
20ddbd7368 STM32F0: Add support for HSI48 2017-04-20 11:08:23 -06:00
Gregory Nutt
a98cdc7a45 Add STM32F0 USB device header file; Update TODO list. 2017-04-20 09:31:12 -06:00
Juha Niskanen
9d0ecedf7d Add support for STM32L152CC, STM32L152RC and STM32L152VC. Update some bits and comments for other STM32L1 parts in chip.h 2017-04-20 06:30:26 -06:00
Juha Niskanen
e631ee4582 STM32 L1: stm32l15xx_rcc: Allow board to configure HSE clock in bypass-mode. Allows using MCO output from ST-link chip (on Nucleo and Discovery boards) as HSE input. 2017-04-20 06:28:01 -06:00
Ian McAfee
6a2c43b0c1 SAMV7 EMAC: Add conditional logic to account the fact that the SAMV71 has 6 rather than 3 queues after version 1. 2017-04-19 14:32:28 -06:00
David Sidrane
29fe0a1b5f Merged in david_s5/nuttx/upstream_stm32_warn (pull request #323) 
stm32:stm32_serial fixed warning

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-04-18 22:01:02 +00:00
David Sidrane
4844011b9c stm32:stm32_serial fixed warning 2017-04-18 11:51:56 -10:00
David Sidrane
a0c4254168 Kinetis:Fixed warning 2017-04-18 10:04:54 -10:00
Gregory Nutt
27e212a291 Nucleo-F072RB: Various fixes to get the first clean build. 2017-04-18 10:37:05 -06:00
Gregory Nutt
b45472baf8 Nucleo-F072RB: Add board configuration 2017-04-18 10:07:03 -06:00
Gregory Nutt
8420e68a9b STM32F0: The STM32F2 does not have use alternate function groupings as does the F1. Rather, it is like other members of the STM32 family with An alternate setting AF0-AF7 for each pin. 2017-04-18 08:40:14 -06:00
Gregory Nutt
04ebdbb336 Move: CONFIG_ADC_NO_START_CONV from drivers/adc/Kconfig to arch/arm/src/stm32[f7]/Kconfig as STM32[F7]_ADC_NO_START_CONV. Refresh all configurations with any reference to CONFIG_ADC_NO_START_CONV. 2017-04-18 07:16:35 -06:00
Juha Niskanen
3c0f3ea35b STM32F7: stm32_adc: Do not override ADCPRE_DIV when measuring internal voltage 2017-04-18 06:51:20 -06:00
Juha Niskanen
54eae7dcde STM32F7: warn if no DMA2 configured when using ADC with DMA. Also correct ADC channel numbers that DMA callback passes to upper half driver. 2017-04-18 06:49:51 -06:00
Gregory Nutt
de22d24f8e More changes UART to USART. Fix garbage code in stm32f0_serial.h that was clearing HAVE_USART 2017-04-17 18:37:52 -06:00
Gregory Nutt
924f58fb2b STM32F0: Change HAVE_UART to HAVE_USART 2017-04-17 17:53:04 -06:00
Gregory Nutt
acdc26f972 STM32F0: Add logic to enable other USARTs. No UART4/5. Rather USART4/5. 2017-04-17 17:51:05 -06:00
Gregory Nutt
639bf31eb4 Move enabling of GPIO peripherals form UART setup to clockconfig. This is not a UART function. It is needed by all periphrals. 2017-04-17 17:20:55 -06:00
Gregory Nutt
8b157b034d STM32F0: Fixes to get STM32F0-Discovery build again after changes to support the STM32F07x 2017-04-17 17:13:32 -06:00
Gregory Nutt
2c01aaad59 STM32F0: Add basic support for STM32F07x family 2017-04-17 16:54:07 -06:00
Alan Carvalho de Assis
b0597583da Fix System Clock value to 48MHz and remove MCLK definition 2017-04-17 12:48:07 -06:00
Alan Carvalho de Assis
735f4d6ea5 STM32F0: Enable the clock for all GPIO ports 2017-04-17 09:58:04 -06:00
Gregory Nutt
cd62425433 STM32F0: type of regval should be uint32_t in clockconfig(). Fix a warning from __start(). 2017-04-17 09:17:31 -06:00
Gregory Nutt
55faedb40d STM32F0: Ooops Missing semicolon 2017-04-17 08:57:00 -06:00
Gregory Nutt
0d9395588b STM32F0: Fix an error in clockconfig() 2017-04-17 08:50:03 -06:00
phreakuencies
eac049222c STM32: Provide TIM5 definition for STM32F429 2017-04-15 12:10:42 -06:00
Gregory Nutt
78bc1aa6bc Argument of network device IOCTL should be unsigned long, just as will all other IOCTL methods. 2017-04-15 09:33:27 -06:00
Simon Piriou
11d3db5c35 photon: add sdpcm + thread support for wlan 2017-04-15 11:39:13 +02:00
Alan Carvalho de Assis
03cbf21cd8 Replace HAVE_USART with HAVE_UART 2017-04-14 11:44:51 -06:00
Alan Carvalho de Assis
4602212612 Fix serial compilation issues 2017-04-14 11:42:20 -06:00
Gregory Nutt
879273f63e arch/arm/Kconfig: Add option for STM32F0 2017-04-14 09:32:15 -06:00
Alan Carvalho de Assis
2cc7744b0c Add stm32f0discovery board support 2017-04-14 08:34:38 -06:00
Gregory Nutt
c910334ced Make sure that Alan is listed as author in new files. 2017-04-14 08:34:37 -06:00
Alan Carvalho de Assis
c3e0ec369f Add basic support for STM32F0 2017-04-14 08:34:36 -06:00
Sebastien Lorquet
dc2890904d STM32L4 DMA: Correct bad channel definition. 2017-04-12 10:25:51 -06:00
Alan Carvalho de Assis
a58823c449 STM32XX: Fix Pending Register definition 2017-04-11 06:45:45 -06:00
Jussi Kivilinna
4c99a6aeec STM32F7: serial: do not stop processing input in SW flow-control mode 2017-04-11 06:40:44 -06:00
Jussi Kivilinna
e9a8dc7c6e STM32F7: serial: disallow broken configuration combination of CONFIG_STM32F7_FLOWCONTROL_BROKEN=y and CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS not set. 2017-04-11 06:39:27 -06:00
Gregory Nutt
ebd2416f9d stm32 COMP: Logic in stm32_comp.h must be configured on CONFIG_STM32_COMP or otherwise it causes an error via #error on every platform without COMP support. 2017-04-09 11:47:57 -06:00
Masayuki Ishikawa
b4e01ecbf9 Merged in masayuki2009/nuttx.nuttx/fix_efm32_i2c_timeout (pull request #312) 
EFM32 I2C: Fix timeout calculation

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-04-06 22:59:34 +00:00
Jussi Kivilinna
e3b3e57e56 RTC: add interface for check if RTC time has been set 
New interface allows checking if RTC time has been set.  This allows to application to detect if RTC has valid time (after
reset) or should application attempt to get real time by other means (for example, by launching ntpclient or GPS).
 2017-04-06 09:53:11 -06:00
Gregory Nutt
ac8ddf4eb1 SAMv7: In review of last patch, change literal 0xfff to WDT_MR_WDD_MAX for portability. 2017-04-06 09:46:04 -06:00
Frank Benkert
571f3d952e SAMV7: Watchdog: fix Forbidden Window Value 
According the Datasheet the WDD Value is the lower bound of a so called Forbidden Window and to disable this we have to set the WDD
Value greater than or equal to the WDV Value.  This seems to be a bug in the datasheet. It looks like we have to set it to a greater value than the WDV to realy disable this Thing.  When triggering the Watchdog faster than the (very slow) clock source of the Watchdog fires, this Forbidden Window Feature resets the System if WDD equals to WDV.

This Changeset disables the Forbidden Window by setting the WDD Value to the Maximum (0xfff) Value possible.
 2017-04-06 09:43:07 -06:00
Jussi Kivilinna
0aa52d98a2 STM32F7: add warning for RXDMA + IFLOWCONTROL combination 
Combination of RXDMA + IFLOWCONTROL does not work as one might expect.
Since RXDMA uses circular DMA-buffer, DMA will always keep reading new
data from USART peripheral even if DMA buffer underruns. Thus this
combination only does following: RTS is asserted on USART setup and
deasserted on shutdown and does not perform actual RTS flow-control.

Data loss can be demonstrated by doing long up_mdelay inside irq
critical section and feeding data to RXDMA+IFLOWCONTROL UART.
 2017-04-06 08:47:45 -06:00
Jussi Kivilinna
e2702cbe4e STM32F7: fix UART7 and UART8 IFLOWCONTROL options 2017-04-06 08:46:24 -06:00
Jussi Kivilinna
dabf45f100 STM32F7: default CONFIG_STM32F7_DMACAPABLE to 'n'. STM32F7 does not have CCM RAM but DTCM, so this option does not need to enabled. DTCM RAM is DMA-able through CPU AHBS bus. 2017-04-06 08:44:53 -06:00
Jussi Kivilinna
e180522854 stm32f7: serial: add interface to get uart_dev_t by USART number, stm32_serial_get_uart 2017-04-06 08:41:41 -06:00
Alan Carvalho de Assis
95941b4908 STM32: Fix SYSCFG_CFGR1_I2C_PBXFMP_SHIFT value 2017-04-06 08:35:33 -06:00
Masayuki Ishikawa
f5b6ae627d EFM32 I2C: Fix timeout calculation 2017-04-06 17:12:13 +09:00
Simon Piriou
e5c4a28c3a photon: wlan support 2017-04-05 21:55:21 +02:00
Juha Niskanen
3e6b92d5fa tm32: stm32l15xxx_rcc: configure medium performance voltage range and zero wait-state when allowed by SYSCLK setting 
Zero wait-state for flash can be configured when:
 Range 1 and SYSCLK <= 16 Mhz
 Range 2 and SYSCLK <= 8 Mhz
 Range 3 and SYSCLK <= 4.2 Mhz

Medium performance voltage range (1.5V) can be configured when SYSCLK is up to 16 Mhz and PLLVCO up to 48 Mhz.
 2017-04-05 07:41:25 -06:00
Juha Niskanen
bff341fdfc stm32: stm32l15xx_rcc: add support for using MSI as system clock 2017-04-05 07:41:24 -06:00
Juha Niskanen
9a29b9a327 stm32: stm32_flash: add EEPROM writing for STM32L15XX 2017-04-04 07:38:49 -06:00
no1wudi
8fbd8b9e6f STM32:add I2C3 SDA pin mapping for STM32F411 2017-04-04 11:57:45 +08:00
no1wudi
730b674b01 STM32:add I2C3 SDA pin mapping for STM32F411 2017-04-04 11:50:58 +08:00
Juha Niskanen
e320e5c100 STM32: add STM32L162VE to chip.h 2017-04-03 07:59:11 -06:00
Juha Niskanen
3a6bd901e4 stm32: fix IWDG and WWDG debug mode stop for STM32L15XX 2017-04-03 07:45:09 -06:00
Gregory Nutt
fb42844788 STM32: Fix a comment 2017-04-02 12:32:20 -06:00
David Sidrane
97fa617c89 stm32f7:stm32_sdmmc removed stray semicolon 2017-03-31 13:17:34 -10:00
David Sidrane
fbb6cfc79c stm32f7:Serial fix for dropped data 
1) Revert the inherited dma bug from the stm32
     see df9ae3c13f
     for details.

  2) Most all CR1-CR3 settings can not be configured while UE
     is true. Threfore we make all operation atomic and disable
     UE and restore it's originalstate on exit.
 2017-03-31 13:17:34 -10:00
Jussi Kivilinna
41912ed98c STM32F7: add support for LSE RTC and enable RTC subseconds 2017-03-31 10:13:40 -06:00
Gregory Nutt
7b789f57ac Review of previous commit 2017-03-30 12:28:40 -06:00
Konstantin Berezenko
95cbbf552b Change STM32 tickless to use only one timer 2017-03-30 10:40:05 -07:00
Juha Niskanen
5577f58458 STM32 RNG: Fix semaphore initial value and disable priority inheritance 2017-03-29 07:12:19 -06:00
Juha Niskanen
9f3b24a4a1 STM32 F7: add stm32 RNG support. This is copied from stm32l4. Tested on STM32F746ZG board. 2017-03-29 07:08:10 -06:00
Gregory Nutt
92da8068ed Merge branch 'master' of bitbucket.org:nuttx/nuttx 2017-03-26 06:57:35 -06:00
Mateusz Szafoni
62f9ae0852 Merged in raiden00/nuttx (pull request #300) 
STM32 COMP cosmetics

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-03-26 12:21:32 +00:00
raiden00pl
f3367233b6 stm32_comp.c: typo 2017-03-26 09:36:53 +02:00
raiden00pl
c1090164f5 stm32/Kconfig: update COMP and OPAMP definitions 2017-03-26 09:34:17 +02:00
raiden00pl
6594c65a77 stm32_comp.c: cosmetic 2017-03-26 09:30:23 +02:00
Gregory Nutt
7d57a2b2bd Trivial changes from review of last PR. 2017-03-25 10:38:41 -06:00
Mateusz Szafoni
c174074dd8 Merged in raiden00/nuttx (pull request #299) 
Add COMP character driver

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-03-25 16:29:02 +00:00
Gregory Nutt
602546f852 Minor typo fix 2017-03-25 10:23:53 -06:00
raiden00pl
a806aedb13 STM32F33: Support for COMP character driver 2017-03-25 16:57:43 +01:00
Alexander Oryshchenko
61ff3c6b84 I needed to use DS3231, I remember that in past it worked ok, but now for stm32f4xx is used another driver (chip specific, stm32f40xxx_i2c.c) and DS3231 driver doesn't work. After investigating a problem I found that I2C driver (isr routine) has a few places there it sends stop bit even if not all messages are managed. So, e.g., removing stm32_i2c_sendstop (#1744) and adding stm32_i2c_sendstart after data reading helps to make DS3231 working. Verified by David Sidrane. 2017-03-24 06:44:33 -06:00
Aleksandr Vyhovanec
82a84a8d98 Merged nuttx/nuttx into master 2017-03-24 11:40:09 +03:00
no1wudi
4c6680df99 Merged in no1wudi/nuttx (pull request #291) 
fix compile error when disabled the flash data cache corruption for stm32 f1xx

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-03-24 00:58:26 +00:00
no1wudi
fd76a3db05 fix spacing 2017-03-24 08:52:46 +08:00
no1wudi
5797e84893 Merged nuttx/nuttx into master 2017-03-24 08:40:40 +08:00
David Sidrane
66910577be stm322_flash:missing unlock on F1 HSI off path 2017-03-23 14:22:45 -10:00
David Sidrane
7e3bec635b stm32_i2c_alt:Move def of regval to top func def per CS 2017-03-23 11:50:37 -10:00
David Sidrane
d25f8710d2 stm32f40xxx_i2c:Duplicate non CS dev of regval 2017-03-23 11:37:12 -10:00
David Sidrane
f5cf22d871 stm32_i2c_alt:Duplicate non CS dev of regval 2017-03-23 11:36:44 -10:00
David Sidrane
c2a1b719be stm32_flash:Need conditinal on non F4 targets 2017-03-23 11:33:32 -10:00
rg
9353ca6039 STM32 I2C: Do not allow CONFIG_I2C_POLLED and CONFIG_I2C_DMA 2017-03-23 11:24:18 -06:00
Aleksandr Vyhovanec
06af125e45 The interrupt occurs over the counter overflow 2017-03-23 17:34:45 +03:00
no1wudi
45f5d30e2e fix compile error when disabled the flash data cache corruption for stm32 f1xx 2017-03-23 13:38:26 +08:00
David Sidrane
c73b65c9b9 stm32f7:stm32_allocateheap.c There are 5 configurations 2017-03-22 23:56:54 +00:00
Gregory Nutt
3fb0a00c35 Small changes from review of last PR. Plus spacing and typo fix. 2017-03-22 17:32:52 -06:00
Gregory Nutt
947acd6c1a Small changes from review of last PR 2017-03-22 15:53:12 -06:00
José Roberto de Souza
b9b4f184a7 stm32: Add workaround for flash data cache corruption on read-while-write 
This is a know hardware issue on some STM32 see the errata of your model
and if you make use of both memory banks you should enable it.
 2017-03-22 13:14:19 -07:00
José Roberto de Souza
09f70c462d stm32: Make up_progmem thread safe 
Writing to a flash sector while starting the erase of other sector
have a undefined behavior so lets add a semaphore and syncronize
access to Flash registers.

But for the semaphore to work it needs to be initialized so each
board needs call stm32_flash_initialize() on initialization, so
to avoid runtime problems it is only using semaphore and making
it thread safe if initialized, after all boards starts to call
stm32_flash_initialize() we can remove the boolean and the check.
 2017-03-22 13:14:15 -07:00
José Roberto de Souza
80f56e75f9 stm32: Fix erase sector number for microcontrolers with more than 11 sectors 
Erase a sector from the second bank cause the bit 4 of SNB being set
but never unsed, so trying to erase a sector from the first bank
was acually eraseing a sector from the second bank.
 2017-03-22 12:42:20 -07:00
David S. Alessio
7f2c4c4274 XMC4xxx: Add FPU support 2017-03-22 12:04:32 -06:00
Gregory Nutt
3f3aa73b8f XMC4xxx: USIC SCTR register, appears taht both WLE and FLE fields hold value - 1. 2017-03-21 17:51:55 -06:00
Gregory Nutt
ea93357a1e XMC4xxx: Fix a typo in the SCU header file 2017-03-21 17:05:47 -06:00