zhengshaobo1
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6e6ba062fd
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clock flags add CLK_OPS_PARENT_ENABLE, parents need enable during gate/ungate, set rate and re-parent
Signed-off-by: zhengshaobo1 <zhengshaobo1@xiaomi.com>
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2023-09-19 10:34:48 +08:00 |
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zhengshaobo1
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be767dde01
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vela fs procfs add clock procfs entry
procfs enrty add clock feature procfs operations
Signed-off-by: zhengshaobo1 <zhengshaobo1@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2023-09-19 10:34:48 +08:00 |
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zhengshaobo1
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09a81017b8
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To solve the problem of unordered setting of div & mux, after solving the problem, the frequency will be set to mux first, and then div
Signed-off-by: zhengshaobo1 <zhengshaobo1@xiaomi.com>
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2023-09-10 13:36:16 +03:00 |
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dongjiuzhu1
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afec562fbb
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drivers/clk: support using clk function at interrupt and idle
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
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2023-07-28 07:12:51 -07:00 |
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liaoao
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a44f498842
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rpmsgclk: allow client to disable clk of server
Signed-off-by: liaoao <liaoao@xiaomi.com>
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2023-07-28 06:57:29 -07:00 |
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lilei19
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38f64f559d
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change strcpy to strlcpy
Signed-off-by: lilei19 <lilei19@xiaomi.com>
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2023-02-24 12:15:40 +08:00 |
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anjiahao
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b88a8cf39f
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use rmutex inside of all repeated implementation
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
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2022-05-30 19:43:48 +08:00 |
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zhuyanlin
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565964a12f
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driver: add clk framework
N/A
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
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2021-12-07 01:35:45 -06:00 |
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