This commit adds deifiniton of get_timer_period() and adj_timer_period()
functions used by adjtime() interface.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds Linux like adjtime() interface that is used to correct
the system time clock if it varies from real value. The adjustment is
done by slight adjustment of clock period and therefore the adjustment
is without time jumps (both forward and backwards)
The implementation is enabled by CONFIG_CLOCK_ADJTIME and separated from
CONFIG_CLOCK_TIMEKEEPING functions. Options CONFIG_CLOCK_ADJTIME_SLEWLIMIT
and CONFIG_CLOCK_ADJTIME_PERIOD can be used to control the adjustment
speed.
Interfaces up_get_timer_period() and up_adj_timer_period() has to be
defined by architecture level support.
This is not a POSIX interface but derives from 4.3BSD, System V.
It is also supported for Linux compatibility.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
fix the problem that stat fails to use the relative path
An error will be reported if used in the following way:
stat("//./bin", &st);
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Store the old environment in a local context so another temporary address
environment can be selected. This can happen especially when a process
is being loaded (the new process's mappings are temporarily instantiated)
and and interrupt occurs.
When l2cc is already in disable state, performing a disable operation
again will flush incorrect cache data to memory
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Invalidate operations at DDI0246H_l2c310_r3p3_trm:
If there is a stale entry in the L2 cache, the system enables the invalidation of
the L1 cache. But before the controller invalidates the L2 cache, it allocates a
line from the L2 cache to an L1 cache.
The robust code sequence for invalidation with a non-exclusive cache arrangement is:
1. InvalLevel2 Address ; forces the address out past level 2
2. CACHE SYNC ; Ensures completion of the L2 inval
3. InvalLevel1 Address ; This is broadcast within the cluster
4. DSB ; Ensure completion of the inval as far as Level 2.
This sequence ensures that, if there is an allocation to L1 after the L1 invalidation, the data
picked up is the new data and not stale data from the L2
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
The current implementation requires the use of enter_critical_section, so the source code needs to be moved to kernel space
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
- This commit adds sabre-6quad:netnsh_ar8031 configuration
Impact:
- None
Testing:
- Tested with ping, telnet, iperf
- Note that iperf in TCP mode still has a performance issue.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- This commit applies the changes from imxrt
- See 3a4542f3c4
Impact:
- imx6 ethernet with d-cache
Testing:
- Tested with imx6_with_ar8031 (will be added later)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
ROM symbols provided by linker are placeholders for addresses
and not a pure addresses, so we need to read data pointed by
ROM symbols instead of using those as pure addresses.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
pthread_cond_wait is preempted after releasing the lock, sched_lock cannot lock threads from other CPUs, use enter_critical_section
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Use double delim to fix windows native build and give an error:
makefile:132: *** target mode do not include“%”. stop.
In Windows environment DELIM := $(strip \) but \ has two role:
first: \ as directory, and second \ as Escape character, Reference:
https://github.com/apache/nuttx/pull/7572#discussion_r1028219229
Signed-off-by: chao an <anchao@xiaomi.com>
If CONFIG_MM_CUSTOMIZE_MANAGER enabled on sim, malloc/mmap is bypassed to glibc, so the memory allocated without execution permisson.
For this case, CONFIG_ARCH_USE_TEXT_HEAP can be used.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
