zhongan
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657d1c9fdc
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Add and fix CSR macros listed in RISC-V spec V1.10.
Add csr operatiing macros.
Change-Id: Ia5c148d10709c21424c5ecaaca01b7d200fb8e01
Signed-off-by: zhongan <zhongan@xiaomi.com>
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2020-09-21 07:35:56 -07:00 |
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Nathan Hartman
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679b4fbee2
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arch: Fix included directed -> included directly
This typo had been copied and pasted into numerous irq and syscall
headers.
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2020-04-05 22:31:15 +01:00 |
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Xiang Xiao
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68951e8d72
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Remove exra whitespace from files (#189)
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
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2020-01-31 09:24:49 -06:00 |
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Ken Pettit
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201a32cf8c
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Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
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2016-10-16 09:47:07 -06:00 |
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