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17992 Commits

Author SHA1 Message Date
Sara Souza
67d29e7537 xtensa/esp32: initialize RTC in case PM or RTC configs are not set, but RWDT is. 2021-08-10 11:15:51 -03:00
zhuyanlin
5820972727 arch:xtensa: add arch stdarg.h include file for xtensa 
Add arch/include/stdarg.h for xtensa.

Change-Id: Ia914ca0f4c95e86b130983ce690479a994a08b56
 2021-08-09 17:58:25 -03:00
Xiang Xiao
776458143c fs/hostfs: Support fchstat and chstat callback 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-09 17:55:44 -03:00
Xiang Xiao
7e0db977cc arch/arm: Add CONTROL register bit field definition 
and replace all hardcode value

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-08-07 09:20:10 -03:00
Daniel P. Carvalho
a7be1c9a2e stm32_pmw: fix pwm_stop() function to enable multiple PWM start and stop. 2021-08-05 14:48:44 -03:00
Michal Lenc
a3986eeba3 arch/arm/src/imxrt/imxrt_flexpwm.c: Set LDOK bits after all channels are set 
This commit changes the FLexPWM driver for iMXRT MCU so that LDOK bits in
Master Control Register are set at once after all channels are configured.
Setting LDOK bit enables the driver to load prescaler, modulus and PWM
values of corresponging submodule and start PWM output. Setting all bits
at once instead of doing it separately can help avoiding the channels to
be out of sync with each other.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-08-05 09:57:49 -07:00
zhuyanlin
ec17cad69d arch:xtensa:include chip/irq.h instead of depend on chip config. 
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.

Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
 2021-08-05 10:08:48 +02:00
zhuyanlin
cec6aeb059 arch:xtensa:vector: fix typo error in level4_ventor 
Change-Id: I66cd3ff30e50e18ed718499aef609dd7aeb82dd3
 2021-08-04 20:16:41 -07:00
zhuyanlin
51d13df317 arch: xtensa: save current SP before overwrting in dispatch_c_isr. 
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.

Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
 2021-08-04 20:16:41 -07:00
Daniel P. Carvalho
2593089f84 stm32_dac: add support for DAC3 2021-08-04 20:22:58 +02:00
zhuyanlin
4fc5b62ec3 arch:xtensa: use letter 'i' in inline assemble constraint instead of I 
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.

Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
 2021-08-04 18:23:40 +02:00
zhuyanlin
9a34705b80 arch:xtensa_testset: remove include arch/spinlock.h 
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.

Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
 2021-08-04 18:18:11 +02:00
zhuyanlin
355133f218 arch:xtensa: add new GNU toolchain for xtensa. 
Add support xcc,xclang GUN toolchin in xtensa,
ESP toolchain is default.

Change-Id: Id00bcf4a16c1e16862a106db32b1da3f3713a14c
 2021-08-04 18:16:14 +02:00
Xiang Xiao
6a396eb224 Fix the printf warning after off_t change 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Id46daa2ee690a73d3187b479f0e7ab0e2e361764
 2021-08-04 06:48:30 -07:00
Abdelatif Guettouche
238a96e7de arch/esp32_cpuint.c: Simplify up_disable/enable_irq. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
4f2f2ef9fb arch/xtensa: Get the cpu member out of the read only structure. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
239f0e257b arch/xtensa/esp32: Keep track to which CPU the interrupt was attached. 
This is used when dettaching.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
0ca5fb4edc arch/xtensa/esp32: When calling up_cpu_index no need to check if in SMP 
mode.  up_cpu_index already does that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
3e44c347fd arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an 
interrupt.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
licheng
431df45e97 EXC_SECURE and SECURE_STACK just can clear at TRUSTZONE_NONSECURE 2021-08-02 23:20:34 -07:00
Alexander Lunev
95abf562f4 boards: added a basic support for chipKIT Wi-FIRE board; 
added Sourcery CodeBench Lite for MIPS ELF Toolchain option;
corrected inaccuracies in Photon board and EMW3162 board README.txt files.
 2021-08-01 08:45:02 -07:00
buyuer
ae3709819c Use exit func iml host_abort. 
When use poweroff command,host_abort will be called,but may be make __stack_chk_fail irq, and host_abort be called in PANIC(), so bring infinite loop, in turn it can not exit SIM.

Signed-off-by: buyuer <dingddding@163.com>
 2021-07-31 08:02:10 -07:00
Xiang Xiao
5d1a444812 Replace __attribute__ ((unused)) with unused_code 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
69df58c2e8 Replace __attribute__((no_instrument_function)) with noinstrument_function; 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
7bcd29dae0 Replace __attribute__((naked, no_instrument_function)) with naked_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
919f8a9a72 Define __ramfunc__ to "locate_code(".ramfunc") farcall_function noinline_function" 
instead of "__attribute__ ((section(".ramfunc"),long_call,noinline))"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
21b69cfd5d Replace all __attribute__((weak)) with weak_data/weak_function 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Xiang Xiao
b3f9ffbe72 Replace all __attribute__((aligned(x)) with aligned_data(x) 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-07-29 21:55:21 -03:00
Gustavo Henrique Nihei
a7a922611b xtensa/esp32: Enable the allocation of multiple SPI Flash partitions 
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-29 20:17:13 +02:00
Alexander Lunev
98e7776714 pic32mz: added support for PIC32MZ2048EFG MCU 2021-07-29 07:46:26 -07:00
raiden00pl
f9937b28cc stm32g4: add CORDIC driver 2021-07-28 14:23:13 -03:00
raiden00pl
6128b298ee stm32g4: add CORDIC definitions 2021-07-28 14:23:13 -03:00
Sara Souza
cdbfacc1fe risc-v/esp32-c3: Adds systimer support and make rt_timer rely on it 2021-07-27 20:43:34 -07:00
Sara Souza
857414e95d xtensa/esp32: expose SPI2 as a char driver 2021-07-27 09:55:49 -07:00
Michal Lenc
9fc806984c adc: add ioctl command to get the number of configured channels 
Number of configured ADC channels is currently only defined in board
level section, typically in xxx_adc.c file. This commit introduces
ioctl command ANIOC_GET_NCHANNELS that returns the number of configured
channels which is determined by the driver code. The change can allow the
applications to be more flexible when it comes to multiple ADC devices
with different number of configured channels.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-26 19:45:47 -07:00
Sara Souza
400d927011 xtensa/esp32s2: Disable wdt and wrap it. 2021-07-26 19:44:30 -07:00
Sara Souza
0794991a07 risc-v/esp32-c3: Disable wdt in the start function. 2021-07-26 19:44:30 -07:00
Sara Souza
5baeb7430b xtensa/esp32: Wrap wdt deinitialization in a function 2021-07-26 19:44:30 -07:00
Jiuzhu Dong
7e393762a7 sim/rptun: optimize multi-core startup and don't need to wait each other. 
Change-Id: I6172823c84a96e4082fa5f33bdb05d7bd1d3b056
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 19:38:07 -07:00
Gustavo Henrique Nihei
2d676f5e46 xtensa/esp32: Enable configuration of GPIO pad's drive strength 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-07-26 19:37:06 -07:00
Jiuzhu Dong
e98220c81a sim/cmdline: save boot cmdline to g_argc g_argv 
Change-Id: I989850a09528e3868957284c9f419d0992ae8d1f
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 19:35:58 -07:00
Xiang Xiao
5e01fe050a arch/sim: Copy include/nuttx/config.h to the local folder 
so the source code compiled by host environment can include config.h
directly and then avoid pass Kconfig option through Makefile manually

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ic9fe6f846082cef2d0808dc717df8ae6ed929edf
 2021-07-27 07:44:33 +09:00
Xiang Xiao
3488a98bd7 sim: Correct the typedef in nuttx/hostfs.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I5fbfd519417c5686325822549c068b1d42f83946
 2021-07-27 07:44:33 +09:00
Jiuzhu Dong
5029712283 renesas/rx65n: add long type for all PRI*PTR 
Error: wqueue/kwork_thread.c:202:3: error: format '%x' expects argument of type 'unsigned int',
 but argument 4 has type 'long unsigned int' [-Werror=format=]
    snprintf(args, 16, "0x%" PRIxPTR, (uintptr_t)wqueue);

Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-07-26 08:44:05 -07:00
Michal Lenc
7354ab187e pwm: add option to break the loops when using multiple PWM channels 
PWM drivers currently use channel number 0 for the channels that are not
used by the application. This commit adds number -1 which indicates that
all following channels are not configured and that the loop can be broken.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-07-26 10:34:16 -03:00
Nathan Hartman
b92aeb8209 Fix various typos 
arch/arm/src/eoss3/eoss3_serial.c:
arch/arm/src/imxrt/hardware/imxrt_flexcan.h:
arch/arm/src/imxrt/imxrt_flexcan.c:
arch/arm/src/imxrt/imxrt_flexpwm.c:
arch/arm/src/imxrt/imxrt_lpi2c.c:
arch/arm/src/kinetis/kinetis_flexcan.c:
arch/arm/src/nrf52/hardware/nrf52_rtc.h:
arch/arm/src/nrf52/nrf52_clockconfig.c:
arch/arm/src/nrf52/nrf52_radio.c:
arch/arm/src/nrf52/nrf52_tim.c:
arch/arm/src/rtl8720c/amebaz_depend.c:
arch/arm/src/s32k1xx/Kconfig:
arch/arm/src/s32k1xx/s32k1xx_flexcan.c:
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c:
arch/arm/src/sama5/hardware/sam_sdmmc.h:
arch/arm/src/sama5/sam_gmac.c:
arch/arm/src/samd5e5/sam_wdt.c:
arch/avr/src/avr32/up_exceptions.S:
arch/avr/src/avr32/up_fullcontextrestore.S:
arch/renesas/src/rx65n/rx65n_dtc.c:
arch/renesas/src/rx65n/rx65n_usbhost.c:
arch/risc-v/src/esp32c3/esp32c3_tickless.c:
boards/arm/stm32h7/stm32h747i-disco/include/board.h:
include/nuttx/lcd/ili9225.h:
libs/libc/stdio/lib_fgetpos.c:
libs/libc/stdio/lib_fseek.c:
libs/libc/stdio/lib_fsetpos.c:

    * Fix typos.
 2021-07-25 18:36:53 -07:00
hartmannathan
c475a71d1c Update arch/arm/src/stm32/Kconfig 
Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com>
 2021-07-25 14:16:22 -03:00
hartmannathan
bb5f302361 Update arch/arm/src/stm32l5/stm32l5_serial.c 
Co-authored-by: saramonteiro <saramonteirosouza44@gmail.com>
 2021-07-25 14:16:22 -03:00
Nathan Hartman
f617c27a8c arch: arm: stm32, stm32f0l0g0, stm32h7, stm32l4, stm32l5: Fix typos. 
arch/arm/src/stm32/stm32_foc.c,
arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h,
arch/arm/src/stm32h7/stm32_allocateheap.c,
arch/arm/src/stm32h7/stm32_fmc.c,
arch/arm/src/stm32h7/stm32_pmstandby.c,
arch/arm/src/stm32h7/stm32_spi.h,
arch/arm/src/stm32h7/stm32_spi_slave.c,
arch/arm/src/stm32h7/stm32_wwdg.c,
arch/arm/src/stm32l4/stm32l4_adc.h,
arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h,
arch/arm/src/stm32l5/stm32l5_gpio.c,
arch/arm/src/stm32l5/stm32l5_gpio.h,
arch/arm/src/stm32l5/stm32l5_irq.c,
arch/arm/src/stm32l5/stm32l5_rcc.c,
arch/arm/src/stm32l5/stm32l5_rcc.h,
arch/arm/src/stm32l5/stm32l5_serial.c, and
arch/arm/src/stm32l5/stm32l5_spi.c:

    * Fix typos in comments. No functional changes.
 2021-07-25 14:16:22 -03:00