Yoshinori Sugino
|
aae4e15d9b
|
arch/risc-v/src: Fix nxstyle warnings
No functional changes
|
2020-10-10 11:44:26 +01:00 |
|
Xiang Xiao
|
80277d1630
|
Refine the preprocessor conditional guard style (#190)
|
2020-01-31 19:07:39 +01:00 |
|
Xiang Xiao
|
68951e8d72
|
Remove exra whitespace from files (#189)
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
|
2020-01-31 09:24:49 -06:00 |
|
Gregory Nutt
|
d5bbbba8ad
|
Rename all remaining arch/xxx/src/xxx/chip to arch/xxx/src/xxx/hardware.
|
2019-05-25 09:27:28 -06:00 |
|
Ken Pettit
|
201a32cf8c
|
Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it.
|
2016-10-16 09:47:07 -06:00 |
|