Gregory Nutt has submitted the SGA
Omni Hoverboards has submitted the SGA
David Sidrane has submitted the ICLA
Mateusz Szafoni has submitted the ICLA
Sebastien Lorquet has submitted the ICLA
Paul Alexander Patience has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
pid variable was initialized to -EINVAL to prevent rt_timer_deinit
from delete an invalid kthread. But priv->pid was being overwritten in the
rt_timer_init, so in case of failure to create a kthread, it would
call rt_timer_deinit with a non expected initialization value.
file. This function is already defined in esp_himem and is used only
when that file is built. We don't need another weak function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
The stm32_gpiosetevent calls stm32_configgpio. So
the pin is infact restored to the SDMMC/SDIO D0.
The seconday init, dropped interrupts in a debug
build with HW stack checking on after the GPIO glich
fixes and that was how it was detected.
This prevents gliches on changing to an output mode.
If not the ALT mux can be selecting a IP block that
is drving the line to say 0. Then the output is connected
to that source, then swithced to the correct source.
This prevents gliches on changing to an output mode.
If not the ALT mux can be selecting a IP block that
is drving the line to say 0. Then the output is connected
to that source, then swithced to the correct source.
This prevents gliches on changing to an output mode.
If not the ALT mux can be selecting a IP block that
is drving the line to say 0. Then the output is connected
to that source, then swithced to the correct source. This
produced a 430 nS glich on a F4 @168 Mhz. It was a enough
to corrupt an I2C device with a bus monitor.
This adds the emmcsd driver for the Polarfire Icicle kit.
The driver has been tested with several SD-cards, such as:
- Kingston 32 GB SDS2 Canvas Select Plus
- Kingston MicroSD Canvas Select Plus
- Sandisk Extreme PRO 32 GB
- Transcend 8 GB MicroSD
The internal eMMC hasn't been tested comprehensively.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Summary:
- This commit replaces the critical section with spinlock in cxd56_serial.c
Impact:
- None
Testing:
- Tested with spresense:rndis_smp, spresense:rndis
and spresense:rndis_wifi
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Gregory Nutt has submitted the SGA
Bill Gatliff has submitted the ICLA
as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
The registers may be in window during interrupt.
Flush window stack to stack first.
And fix warning in build.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
Up_getsp may be not inline in gcc, thus get the sp
is up_getsp function's sp, not the caller function.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
Rearchitect video driver:
- Define two video I/F(struct imgsensor_ops_s and struct imgdata_ops_s),
and support them.
- CISIF driver supports new video I/F struct imgdata_ops_s.
- ISX012 driver supports new video I/F struct imgsensor_ops_s.
- Move ISX012 driver to general driver directory.
Repeated automated sercon, serdis on VBUS proved to fail
for CDCACM DATA IN (device Serial TX). The root cause was
that the EP was left active after disconnect. This resulted
in the first serial write falling to kick-off the EP IN request.
That should restart the EP ISR.
Repeated automated sercon, serdis on VBUS proved to fail
for CDCACM DATA IN (device Serial TX). The root cause was
that the EP was left active after disconnect. This resulted
in the first serial write falling to kick-off the EP IN request.
That should restart the EP ISR.
Repeated automated sercon, serdis on VBUS proved to fail
for CDCACM DATA IN (device Serial TX). The root cause was
that the EP was left active after disconnect. This resulted
in the first serial write falling to kick-off the EP IN request.
That should restart the EP ISR.
This commit moves the Wi-Fi initialization to
Wi-Fi specific file and to spiflash initialization.
It also reserves one partition for Wi-Fi use and for general use,
and makes it possible to me mounted by several FS.
functions will call esp32_txint again which leads to deadlock since
esp32_txint has already locked the spinlock.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This reverts commit 45672c269d.
Because:
* It's very confusing to have cc as LD.
* I don't see what "-nostartfiles -nodefaultlibs" in LDFLAGS are
supposed to do when we use LD directly. It would be simpler to
remove them from our LDFLAGS.
Correct typos in include/nuttx/arch.h and suppress
"'noreturn' function does return" warning coming from arm_pthread_exit.c
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This is currently only used on STM32L4+ devices. Page erase in
flash_erase() function supports only dual-bank mode so it makes little
sense to configure this for unsupported single-bank mode.
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
This commit removes the initialization of the Wi-Fi partition
from the Wi-Fi board logic and moves it to the SPI Flash board code.
It creates 2 different partition (one for Wi-Fi and one for general
use).
It also allows these partitions to be mounted over several FSs.
When SIM_SPI is valid, a specified Linux SPI device ‘spidevN.P’(N is bus number and P is CS number) is attached to nuttx simulator, shown as 'spi0' under /dev. One may type spi command (need SPITOOL valid) in NSH to control the Linux SPI and exchange data, other devices such sensors can use it to debug in simulator on a Ubuntu PC. Note that a USB<>SPI module (e.g. CH341A/B) should be plugged in to achieve Linux SPI ports.
Change-Id: I275b2c2bbf6d14bcdf514c89efb9a2264d69e9a3
Signed-off-by: liucheng5 <liucheng5@xiaomi.com>
CAN_ESR2 register was having problems of havng the correct values when
the bus was busy (with 3 and more nods). The register bit fields were
incorrectly indicating that there is no free MB and would not updated
itself from this state which was causing the applications to freeze on
write. This change relies only on a software control which should avoid
the problems described above.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary:
- I noticed that qemu-intel64:nsh does not work
- And I found that commit 6e6eecaa73 affected this issue
- This commit changes idle stack allocation to fix the issue
Impact:
- None
Testing:
- Tested with qemu-intel64:nsh and qemu-intel64:ostest
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.
Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
The PRO CPU and APP CPU have different peripherals for GPIO interrupts.
Each CPU needs to allocate an interrupt and attach it to its GPIO
peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This feature depends on frame pointer, "-fno-omit-frame-pointer" is mandatory
This feature can not be used in THUMB2 mode if you are using GCC toolchain,
More details please refer:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92172
Signed-off-by: chao.an <anchao@xiaomi.com>
Matrix.
This allows manipulating interrupts from both CPUs. Internal interrupts
however, still need to be disabled/enabled by each CPU.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
interrupt.
That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.
All the drivers are also updated with this API change.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This map also keeps track of the CPU that attached the IRQ. This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA
This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.
Signed-off-by: chao.an <anchao@xiaomi.com>
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Consider follow coprocessor configuration case:
\#define XCHAL_CP_NUM 1 /* number of coprocessors */
\#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME "AudioEngineLX"
\#define XCHAL_CP1_IDENT AudioEngineLX
\#define XCHAL_CP1_SA_SIZE 208 /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.
Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
Previous implementation has always expanded the width of the timer to 32-bit.
This feature is not always needed and should be configurable from Kconfig.
This commit changes the FLexPWM driver for iMXRT MCU so that LDOK bits in
Master Control Register are set at once after all channels are configured.
Setting LDOK bit enables the driver to load prescaler, modulus and PWM
values of corresponging submodule and start PWM output. Setting all bits
at once instead of doing it separately can help avoiding the channels to
be out of sync with each other.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Many duplicate code when more chips add-in,
follow arch/arm/include/irq.h method, use chip/irq.h instead.
Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e
In levelx(2,3,4,5)_handler, first need to save sp in a12,
then after dispatch_c_isr we can restore sp from a12.
Change-Id: Idb6b64a782da866670a4db80b33435a9b63f02c3
Some toolchain such as xtensa-xcc is unrecognize with constraint letter 'I',
letter 'i' is more common in GNU assembler.
Change-Id: I00f6a33fd7a5f2b95508c683e9954d402b68755f
In config with no "CONFIG_SPINLOCK", include arch/spinlock.h will lead to
build error as multi definition with spinlock_t. Nuttx/spinlock.h will
include arch/spinlock.h when needed.
Change-Id: I33b48503f679ec79af3a0ef1f0fb1536aaf1ce7c
When use poweroff command,host_abort will be called,but may be make __stack_chk_fail irq, and host_abort be called in PANIC(), so bring infinite loop, in turn it can not exit SIM.
Signed-off-by: buyuer <dingddding@163.com>
Currently the "esp32_spiflash_alloc_mtdpart" allocates a
statically-defined partition from "offset" and "size" set via
Kconfig.
This commit changes the function interface to receive those information
as arguments, enabling the creation of multiple MTD partitions with
different offsets and sizes.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Number of configured ADC channels is currently only defined in board
level section, typically in xxx_adc.c file. This commit introduces
ioctl command ANIOC_GET_NCHANNELS that returns the number of configured
channels which is determined by the driver code. The change can allow the
applications to be more flexible when it comes to multiple ADC devices
with different number of configured channels.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
so the source code compiled by host environment can include config.h
directly and then avoid pass Kconfig option through Makefile manually
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: Ic9fe6f846082cef2d0808dc717df8ae6ed929edf
Error: wqueue/kwork_thread.c:202:3: error: format '%x' expects argument of type 'unsigned int',
but argument 4 has type 'long unsigned int' [-Werror=format=]
snprintf(args, 16, "0x%" PRIxPTR, (uintptr_t)wqueue);
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
PWM drivers currently use channel number 0 for the channels that are not
used by the application. This commit adds number -1 which indicates that
all following channels are not configured and that the loop can be broken.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
arch/arm/src/stm32/Kconfig:
* In configs STM32_ADC_MAX_SAMPLES, STM32_FOC_HAS_PWM_COMPLEMENTARY:
Fix typos in help text.
arch/arm/src/stm32h7/Kconfig:
* In configs STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY,
STM32H7_FLASH_CR_PSIZE, STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY,
and STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY: Fix typos in help text.
arch/arm/src/stm32l5/Kconfig:
* In configs STM32L5_FLOWCONTROL_BROKEN, STM32L5_SDMMC1_DMAPRIO: Fix
typos in help text.
arch/arm/src/stm32/hardware/stm32_exti.h:
* Change STM32_EXTI2_OFFSET (offset to EXTI2 registers) from 0x18
to 0x20. This symbol is defined when CONFIG_STM32_STM32F30XX or
CONFIG_STM32_STM32F33XX. According to the current reference
manuals for STM32F334xx (RM0364 rev 4) and STM32F302xx (RM0365
rev 8), EXTI_IMR1 is at offset 0x00 and EXTI_IMR2 is at offset
0x20, i.e., 0x20 apart. The same offset applies to the rest of
the registers: EMR1/EMR2, RTSR1/RTSR2, etc.
Summary:
- I noticed that sim:smp does not work correctly on macOS
due to the recent changes
- Actually, it can not receive the IPI host signal, so if
a new task is scheduled on CPU1/2/3, it hangs.
- Finally, I found that sim_cpu_start() calls pthread_attr_init()
which locates not on the host OS but on the NuttX
- This commit fixes this issue by adding the symbol names
to nuttx-names.in
Impact:
- sim in SMP mode
- NOTE: stack usage for CPU1/2/3 IDLE is still incorrect on macOS
Testing:
- Tested with ostest on Ubuntu 18.04 (x86_64) and macOS 11.4 (x86_64)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
since this macro isn't check from host side after:
commit cee43ce280
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Fri Jul 16 02:23:59 2021 +0800
arch/sim: Initialize the idle thread stack info correctly
and change the default value of IDLETHREAD_STACKSIZE to 65536
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Summary:
- I noticed that sim:smp does not work correctly on macOS
due to the recent changes
- Actually, it can not receive the IPI host signal, so if
a new task is scheduled on CPU1/2/3, it hangs.
- Finally, I found the issue depends on pthread stack settings
and perhaps it might affect the host signal handling.
- This commit fixes this issue by just reverting the pthread
stack setting only for macOS.
Impact:
- sim:smp on macOS
- Stack usage for CPU1/2/3 IDLE will be incorrect
Testing:
- Tested with ostest on macOS 11.4 (x86_64)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
