We can see them in ifconfig:
ap> ifconfig
wlan0 Link encap:Ethernet HWaddr 42:64:7f:b3:12:03 at UP mtu 1500
inet addr:10.0.1.2 DRaddr:10.0.1.1 Mask:255.255.255.0
inet6 DRaddr: ::
RX: Received Fragment Errors Bytes
00000b9b 00000000 00000000 21daf5
IPv4 IPv6 ARP Dropped
00000a33 00000137 00000031 00000000
TX: Queued Sent Errors Timeouts Bytes
00000ac4 00000ac4 00000000 00000000 1a2103
Total Errors: 00000000
Signed-off-by: meijian <meijian@xiaomi.com>
Since the introduction of the rp2350, the pico-sdk project has been
re-arranged and elf2uf2 has been merged in to a new 'picotool' binary
which is supplied and installed separately.
RDTSCP instruction reads the current value of the processor’s
time-stamp counter (a 64-bit MSR) into the EDX:EAX registers, and it
also reads the value of the IA32_TSC_AUX MSR (address C0000103H) into
the ECX register. However, the current RDTSCP implementation does not
provide a hint for the compiler that ECX has been changed, resulting in
register corrupted and subtle errors.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
Make umm & kmm heap alloc more clear, and possible support FLAT build to
enable kernel heap.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
1. correct the armv8-r fpu flag from vfpv3-d16 to fpv5-sp-d16
2. add neon support
This commit updates the build script to specify the FPU type of
`fpv5-sp-d16` when the processor is configured with a single-precision
FPU, and `neon-fp-armv8` when the processor is configured with a
double-precision + Advanced SIMD-capable FPU.
Note that the `fp-armv8` FPU type is an alias for double-precision FPv5
with 32 double-precision registers (refer to the GCC
`gcc/config/arm/arm-cpus.in` for more details); NEON is always
specified in case of a double-precision configuration because the
Cortex-R52 can only be configured as such.
Reference:
https://developer.arm.com/Processors/Cortex-R52
Instruction set:
Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point
Unit either with single-precision or double precision and Neon.
Signed-off-by: chao an <anchao@lixiang.com>
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
reason:
dynaminc create g_irqmap to reduce the use of data segments
CONFIG_ARCH_NUSER_INTERRUPTS should be one more than the number of IRQs actually used
Signed-off-by: hujun5 <hujun5@xiaomi.com>
In corner case, the pending ISR will be triggered immediately
after enable the IRQ, this PR will setting CPU affinity first
to avoid routing the unexpected IRQ to other CPUs.
Signed-off-by: chao an <anchao@lixiang.com>
Copied spi flash files from risc-v
Removed old spiflash from make.defs
KConfig modifications for common spiflash
Added new spiflash entry to make.defs
S2 Board config update
Modifications working on S2. Need fix on ROM function
Board fixes
Deleted old spiflash files
Fixes for smartfs operation
Set new HAL version
Fixed wrong change on S3
Cache flush must be done prior to the APP cpu initalization. This,
however, must be true for the case where PSRAM is not available or
not selected. To do that, this commit flushs the cache during the
device initialization.
This commit fixes a deadlock in `esp32s3-devkit:sta_softap`
defconfig: `spin_lock_irqsave` was being used to enter a critical
section that calls `nxsem_post`. In this case, it's recommended
to use `[enter|leave]_critical_section` to avoid deadlocks when a
context switch may happen, for instance.
NuttX uses PSRAM, possibly using the APP_CPU cache MMU,
way before starting the APP_CPU in up_cpu_start().
Flushing the cache when launching the APP_CPU can cause
data corruptions on PSRAM.
Eg. mm_heap structures if the PSRAM is added to a heap.
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
This PR configures the BL808 MMU to cache the the User Text, Data and Heap. We enable the T-Head MMU Flags for Shareable, Bufferable and Cacheable, as explained in the previous PR: https://github.com/apache/nuttx/pull/13199
This PR fixes the Slow Memory Access for NuttX Apps on Ox64 BL808 SBC: https://github.com/apache/nuttx/issues/12696. With this fix, Ox64 NuttX CoreMark jumps from 19 to 1,104. (Close to Buildroot Linux CoreMark)
Modified Files:
`arch/risc-v/Kconfig`: Enabled `ARCH_MMU_EXT_THEAD` for BL808 SoC.
