Commit Graph

22195 Commits

Author SHA1 Message Date
Yanfeng Liu
01c37f7012 riscv/rv32m1: fix build issue
This exports `return_from_exception` symbol to fix build issue with
unified in-kernel syscall.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
Yanfeng Liu
6986cd4105 arch/riscv: unify in-kernel syscall
This generalizes the in-kernel syscall approach from KERNEL mode to
all build modes so that to unify in-kernel syscall invocations.  As
a result, machine mode ECALL and the supervisor folder are no longer
needed.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 21:25:59 +08:00
nuttxs
2af8a886ab arch/xtensa/esp32: Replace nxsig_usleep() with up_udelay() to
avoid context switching, and the actual time difference caused
by the setting of TICK in nxsig_usleep() is quite large.
2024-08-08 20:01:46 +08:00
Daniel Jasinski
8399a780d8 build: Fix Toolchain.cmake for CONFIG_SIM_ASAN enabled
This commit adds missing add_link_options to specify sanitizers
also during linking stage.

Signed-off-by: Daniel Jasinski <jasinskidaniel95szcz@gmail.com>
2024-08-08 09:44:47 +08:00
Yanfeng Liu
77cfbf8914 riscv/fork: fix gp register handling
This fixes the handling of gp register in fork.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Yanfeng Liu
3f021d5429 riscv/fork: fix fp/s0 field position
The fp/s0 field position shall be in line with the macro
FORK_FP_OFFSET/FORK_S0_OFFSET.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-08 09:42:29 +08:00
Shoukui Zhang
f94160095e Adapt i2c slave callback interface for rp2040 and s32k11x
Signed-off-by: Shoukui Zhang <zhangshoukui@xiaomi.com>
2024-08-07 12:13:38 -03:00
Ville Juven
622e5b26b3 riscv/syscall: Fix fork() system call
When executing fork() via a system call, the parent's stack gets corrupted
by the child, as during exception return the child loads the parent's
stack pointer from the context save area.

This happens because the full parent stack (including what has been pushed
during the system call) is copied to the child. What should be copied, is
only the user stack of the parent (the kernel stack is not interesting).

Fix this by only copying the parent's user stack to the child; and make
the child return directly to userspace (not via dispatch_syscall).
2024-08-07 02:41:14 +08:00
Ville Juven
2cf8ac2f63 risc-v/riscv_swint.c: Simplify implementation of dispatch_syscall
Simplifies the implementation of dispatch_syscall, making it easier to
understand and maintain. Let the C-compiler do most of the work, instead
of doing everything as inline assembly.
2024-08-07 02:41:14 +08:00
Ville Juven
fa71bc3d74 riscv/syscall: Add dependency to RISCV_PERCPU_SCRATCH when LIB_SYSCALL=y
The per CPU scratch register is needed by system calls -> enable it by
default.
2024-08-07 02:41:14 +08:00
Julian Oes
75c65c7ce9 arch/stm32h7: add defines for USART clock selection
This adds the necessary defines to set the USARTs' kernel clock source
selection.

This is required for a configuration where the bootloader (running
before NuttX) changes the USARTs' clock selection, so they need to be
restored on board init.

This is according to the reference manual RM0399 page 448.
2024-08-06 14:31:21 +08:00
Filipe Cavalcanti
65e989e063 arch/risc-v: add support for motor control on ESP32|C6|H2 2024-08-05 15:35:19 -03:00
Yanfeng Liu
a36c168e54 riscv/nsbi: fix up_udelay for rv32
This fixes riscv_sbi_get_time for rv32 and NuttSBI is used.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-05 16:21:49 +08:00
chao an
4ef3eeb305 arch/x86_64: fix build break if disable CONFIG_SPINLOCK
Create version.h
chip/intel64_irq.c:78:34: error: conflicting type qualifiers for ‘g_irq_spin’
   78 | static spinlock_t                g_irq_spin;
      |                                  ^~~~~~~~~~
In file included from chip/intel64_irq.c:40:
include/nuttx/spinlock.h:168:28: note: previous declaration of ‘g_irq_spin’ with type ‘spinlock_t’ {aka ‘volatile unsigned char’}
  168 | extern volatile spinlock_t g_irq_spin;
      |                            ^~~~~~~~~~
chip/intel64_cpu.c: In function ‘x86_64_cpu_ready_set’:
chip/intel64_cpu.c:314:3: warning: implicit declaration of function ‘spin_lock’ [-Wimplicit-function-declaration]
  314 |   spin_lock(&g_ap_boot);
      |   ^~~~~~~~~
chip/intel64_cpu.c:322:3: warning: implicit declaration of function ‘spin_unlock’; did you mean ‘sched_unlock’? [-Wimplicit-function-declaration]
  322 |   spin_unlock(&g_ap_boot);
      |   ^~~~~~~~~~~

Signed-off-by: chao an <anchao@lixiang.com>
2024-08-05 16:20:47 +08:00
Yanfeng Liu
5848a8e77c riscv/qemu-rv: revise PROTECTED mode
This revises PROTECTED build for qemu-rv mainly to avoid hard-coded
addresses in linker scripts. It also added rv32 support, cleaned up
config `pnsh64` and added config `pnsh`.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-04 11:09:26 +08:00
Yanfeng Liu
cafee0e086 mm/mm.h: add mm_free_delaylist interface
This adds explicit `void mm_free_delaylist(heap)` interface so that
to force freeing the heap's delaylist.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-03 01:30:04 +08:00
Ville Juven
1f928b2338 qemu-rv: Add test target pnsh64 for BUILD_PROTECTED
This adds BUILD_PROTECTED target for rv-virt (rv-virt:pnsh64).
2024-08-02 20:29:11 +08:00
adriendesp
6ef8a73614 arch/xmc4 : fixed critical section in i2c_transfer
The critical section was declared at the wrong place.
The critical section wasn't left if error returned.
2024-08-02 20:28:25 +08:00
Lwazi Dube
a50dc7746c arm: Make ARMv5 boards work again
Fix some bugs found while trying run modern NuttX on an old board.
2024-08-02 13:39:40 +08:00
Yanfeng Liu
918ad10859 riscv/qemu: add NuttSBI support
This adds NuttSBI support for rv-virt device so that to enable CI
checks for NuttSBI later. It allows using `-bios nuttx` option to
run NuttX with QEMU v6.2 w/o OpenSBI.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
ab7bc90ebb riscv/nsbi: halt upon sbi_mexception
This avoids endless restart if NuttSBI fails to enter S-mode.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Yanfeng Liu
5e551632dd riscv/nsbi: prefer PMP settings in device hook
This adjusts sbi_start behavior so that if SBI late initialization hook
is defined, PMP setting is assumed to be fully done in the hook, because
the default PMP operation may fail for various reasons such as lacking
free entries or the default setting doesn't work on devices like QEMU
v6.2.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-08-01 23:32:01 +08:00
Huang Qi
f9cc33468f riscv/espressif: Mark private data as static in esp_spi.c
These symbols only used in esp_spi.c and too simple
to conflict with others, so mark them as static:
- cfg
- ctx
- dev_cfg
- timing_param

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 23:28:53 +08:00
Ville Juven
cbb07a595e k230_start.c: Fix condition for k230_copy_init_data()
Fixes regression from https://github.com/apache/nuttx/pull/12220

Error: chip/k230_start.c:80:13: error: 'k230_copy_init_data' defined but not used [-Werror=unused-function]
   80 | static void k230_copy_init_data(void)
      |             ^~~~~~~~~~~~~~~~~~~
2024-08-01 23:27:30 +08:00
p-szafonimateusz
3c05da536a arch/intel64: add support for HPET as system clock
HPET can be used as system clock for x86_64

to set HPET as system clock you have to enable:
  CONFIG_ONESHOT=y
  CONFIG_ALARM_ARCH=y
  CONFIG_INTEL64_ONESHOT=y
  CONFIG_ARCH_INTEL64_HPET_ALARM=y

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-08-01 17:49:41 +08:00
Tiago Medicci
24954800a7 espressif: Update HAL version for all Espressif SoCs
Provides the most update libraries to support the drivers for the
Espressif SoCs.
2024-08-01 16:04:53 +08:00
Tiago Medicci
54b27c3d32 esp32s3/kconfig: Add more ESP32-S3 modules and fix comments
Other ESP32-S3 modules (with embedded flash and PSRAM) were added.
Also, the `help` section of the Kconfig was updated to better
describe the modules' flash and PSRAM sizes.
2024-08-01 16:04:53 +08:00
Huang Qi
6ea3bc1217 riscv/debug: Add support for steppoint
Steppoint can be implemented by icount(instruction count)
from RISC-V debug extension, but it may not implemented in all RISC-V cores.

Unfortunately, the currently supported RISC-V cores do not implement it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-08-01 13:57:51 +08:00
Eren Terzioglu
00ff9ef15c esp32[c3|c6|h2]: Add SPI slave DMA support 2024-08-01 01:26:29 +08:00
Eren Terzioglu
f5b63cea18 esp32[c3|c6|h2]: Add SPI master DMA support 2024-08-01 01:26:29 +08:00
Inochi Amaoto
b35f7aed48 arch/risc-v: qemu: add AIA support
Implement AIA support for qemu rv-virt.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Inochi Amaoto
5f70307111 arch/risc-v: introduce AIA support
Advanced Interrupt Architecture (AIA) introduces flexiable interrupt
controll for RISC-V. It includes three parts: AIA CSRs, Incoming Message
Signaled Interrupt Controller (IMSIC) and  Advanced Platform-Level
Interrupt Controller (APLIC).

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-31 12:43:04 -03:00
Tiago Medicci
c99c3ceec2 up_copy_section: Improve function description
Add "Input Parameters" section to already existing definitions
and declarations of `up_copy_section` function.
2024-07-31 02:33:12 +08:00
Tiago Medicci Serrano
016bc47a63 esp32s3/elf: Enable ELF loader for ESP32-S3
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
2024-07-31 02:33:12 +08:00
zouboan
d74a612a6e zynq-mpsoc/zcu111: independent JTAG configs from normal nsh configs 2024-07-30 12:41:30 -03:00
p-szafonimateusz
07c1f5db92 arch/intel64/irq.h: rename rdtsc macros
rename _rdtsc macro to rdtsc to avoid conflict with external code
rename rdtsc macro to rdtscp to be the same as asm instruction used

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-30 21:53:08 +08:00
p-szafonimateusz
90e47bf1f5 arch/x86_64/src/intel64/intel64_cpu.c: remove workaround for spin_lock
remove workaround for spin_lock which is no longer needed after inline splinlock change
2024-07-30 21:40:53 +08:00
adriendesp
cd4fdf27c5 arch/xmc4 : i2c driver
Added lower half i2c driver
2024-07-30 18:23:19 +08:00
Yanfeng Liu
a6c7e68b5d riscv/qemu-rv: skip reloading mhartid
As a0 already has mhartid passed by SBI  or ZSBL, no need to load it
again here.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-30 18:20:22 +08:00
Tiago Medicci Serrano
c91599d34c esp32s3/i2s: Fix faulty initialization when SMP is enabled
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
2024-07-30 01:44:57 +08:00
Tiago Medicci Serrano
1ab1a905b8 esp32s3/i2s: Add CONFIG_ESP32S3_I2S_MAXINFLIGHT to Kconfig
Enable setting the number of in-flight buffers to be used by the
I2S peripheral on ESP32-S3 using Kconfig.
2024-07-30 01:44:57 +08:00
anjiahao
bc1083ac33 arm_backtrace_unwind:Make the backtrace search the entire stack as much as possible
also fixbacktrace crash when idle thread lr is random

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-07-29 22:19:56 +08:00
Eren Terzioglu
98f5d6adc5 esp32[s2|s3]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Eren Terzioglu
e467a16abe esp32[c3|c6|h2]: Add temperature sensor support 2024-07-27 14:12:44 -03:00
Henry Rovner
23bc78a5b7 bl808_wdt: Expand function headers 2024-07-27 22:59:23 +08:00
Henry Rovner
42eafcdfa5 risc-v/bl808: Add watchdog driver
This change implements a driver for the two watchdog timers on the BL808, and enables it as part of the timer config. The driver is based on the GP timer driver.
2024-07-27 22:59:23 +08:00
Filipe Cavalcanti
91dfd20eaf arch/xtensa: add support for brushed DC motor control
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Review fixes

arch/xtensa: add support for fault signal on motor control

Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed

Basic bring up ready. New Kconfig options for motor.

Good motor registration

Working on enabling pwm generators

Working on enabling pwm generators

Added fops functions

Success on PWM 50%

stable pwm operation for bdc

Added loopback option for testing

Improved rules on fsm

Working motor direction control

Testing new ISR for fault handling

Issues on fault ISR

Removed fault implementation (not working)

Added support for esp32s3

Documentation improvements

Added default motor spin direction

Added parameter change while running

Got responsive fault indicator

Working brakes - still need to work on starting isr

Fixed single-time ISR initializiation

Working soft brake on fault

Improved KConfig for BDC and BLDC

Kconfig fixed at board level
2024-07-27 12:08:51 +08:00
Huang Qi
d7f82fb14c Correct comment blocks
Fix wrong comment blocks in the following files:
- arch/arm/src/stm32f0l0g0/stm32_pwr.c
- include/nuttx/mtd/nand_config.h

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
Huang Qi
3b70bf7ff0 samv7: Fix comment block in sam_rstc.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-27 03:11:39 +08:00
raiden00pl
e75c19ce58 arch/arm/{nrf53|nrf91}: enable fpu if CONFIG_ARCH_FPU=y
enable fpu if CONFIG_ARCH_FPU=y, the previous condition depended on CONFIG_ARCH_HAVE_FPU=y
2024-07-26 23:46:34 +08:00