Commit Graph

22195 Commits

Author SHA1 Message Date
buxiasen
f5021021ae up_backtrace: fix maybe backtrace the exiting thread
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-07-26 12:03:43 +08:00
Yanfeng Liu
9e59b0b43b riscv/qemu: guard u16550 uses
This guards the uses for u16550 serial initialization, just in case
that no u16550 is configured.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-26 12:01:29 +08:00
Henry Rovner
049a6da098 risc-v/bl808: Add timer driver
This change implements a driver for the hardware timer blocks on the BL808, as well as a config with the timer example enabled.
2024-07-24 10:06:54 +08:00
nuttxs
a83a569652 arch/xtensa/esp32s3: Add qspi/spi_slave/lcd DMA request return value.
Optimize DMA initialization for duplicate calls.
2024-07-23 22:48:24 +08:00
Yanfeng Liu
3b9a346fe7 riscv/nsbi: unblock up_udelay
This fixes the always zero time in NuttSBI case as the `error` field
contains the correct timestamp. This in turn also fixes the block of
`up_udelay()` which further leads to boot failure of `canmv230:master`
config.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-22 23:46:43 +08:00
Inochi Amaoto
0ddcbe62ec arch/risc-v: does not clear IPI address in S mode
According to the riscv-aclint doc, writing 0 to SSWI address
has no effect. Remove this unnecessary write for S mode.

Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 22:59:29 +08:00
YAMAMOTO Takashi
985d395b02 esp32s3_textheap.c: fix a build error w/o CONFIG_ESP32S3_SPIRAM 2024-07-18 16:42:52 +08:00
nuttxs
de3737cd90 arch/xtensa/esp32s3: Deinitialize ESP32-S3 QSPI GDMA engine.
Correctly releasing channels after using QSPI is crucial
to prevent issues caused by multiple requests that may lead
to DMA channel resource conflicts.
2024-07-18 13:41:04 +08:00
chao an
7780cfc5a6 tricore/cmake: add support of cmake build for tricore
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

CMake command:
$ cmake -B build -DBOARD_CONFIG=tc397/nsh -GNinja
$ cmake --build build

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-18 13:40:49 +08:00
Inochi Amaoto
000b0ec4a1 arch/risc-v: make common up_allocate_heap weak symbol
The common `up_allocate_heap` is a strong symbol, which leads to
error when building with CONFIG_DEBUG_LINK_WHOLE_ARCHIVE. Make
`up_allocate_heap` weak function to mitigate this problem.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-07-18 13:40:37 +08:00
Lup Yuen Lee
bdf60d7966 risc-v/bl808, sg2000: Configure MMU to cache Kernel Text, Data and Heap (T-Head C906)
This PR configures the BL808 and SG2000 MMU (inside T-Head C906) to cache the the Kernel Text, Data and Heap.  We set the MMU Flags (Shareable, Bufferable and Cacheable) as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906

This PR fixes the Slow Memory Access for NuttX Kernel in BL808 and SG2000: https://github.com/apache/nuttx/issues/12696

In the next PR, we will fix the Slow Memory Access for NuttX Apps, by caching the User Text and Data.

arch/risc-v/src/bl808/bl808_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for BL808 Kernel Text, Data and Heap

arch/risc-v/src/sg2000/sg2000_mm_init.c: Added MMU Flags (Shareable, Bufferable and Cacheable) for SG2000 Kernel Text, Data and Heap
2024-07-17 12:08:04 -03:00
Yanfeng Liu
d6c67c555f riscv/trap: fix sp restore logic
This fixes stack pointer restore logic to avoid parent stack corruption
by forked child in PROTECTED build.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
Yanfeng Liu
08c4686f47 riscv/fork: fix tp for PROTECTED
This fixes `tp` value of forked child in PROTECTED build to support
vfork. Why? the optimized `dispatch_syscall` requires `tp` to hold
the task TCB since commit e6973c764c.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-17 17:20:00 +08:00
chao an
4db1169e6f arch/tricore: fix compiler warning on GCC toolchain
tc3xx/tc3xx_timerisr.c: In function ‘up_timer_initialize’:
tc3xx/tc3xx_timerisr.c:58:39: warning: passing argument 1 of ‘tricore_systimer_initialize’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   58 |   lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY);
In file included from tc3xx/tc3xx_timerisr.c:31:
nuttx/arch/tricore/src/common/tricore_internal.h:252:35: note: expected ‘void *’ but argument is of type ‘volatile Ifx_STM *’ {aka ‘volatile struct _Ifx_STM *’}
  252 | tricore_systimer_initialize(void *tbase, int irq, uint64_t freq);
      |                             ~~~~~~^~~~~
tc3xx/tc3xx_serial.c:177:16: warning: initialization discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  177 |   .uartbase  = &MODULE_ASCLIN0,
      |                ^
tc3xx/tc3xx_serial.c:178:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  178 |   .pins      = &g_uart0_pins,
      |                ^
common/tricore_trapcall.c: In function ‘tricore_trapcall’:
common/tricore_trapcall.c:66:3: warning: passing argument 4 of ‘_assert’ discards ‘volatile’ qualifier from pointer target type [-Wdiscarded-qualifiers]
   66 |   PANIC_WITH_REGS("Trap", CURRENT_REGS);
      |   ^~~~~~~~~~~~~~~
In file included from common/tricore_trapcall.c:29:
nuttx/include/assert.h:189:45: note: expected ‘void *’ but argument is of type ‘volatile uintptr_t *’ {aka ‘volatile long unsigned int *’}
  189 |              FAR const char *msg, FAR void *regs);

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
chao an
8e20b8d862 arch/tricore: add support of tricore gcc toolchain
Toolchain Upstream:
https://github.com/EEESlab/tricore-gcc-toolchain-11.3.0

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-17 17:18:02 +08:00
zouboan
b817db86b8 zynq-mpsoc: add support for mio/emio 2024-07-16 18:50:52 -03:00
chao an
bc7791e079 arch/tricore: synchronize instruction/data following MTCR/MFCR
Some barrier are necessary to avoid compiler optimizations

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-16 21:13:13 +08:00
GC2020
8f243d3eb7 /rp2040 Rename the RP2040-specific PWM_MULTICHAN definition to avoid confusion with the global PWM_MULTICHAN 2024-07-16 20:09:10 +08:00
shizhenghui
fea727a050 arch/sim/Makefile: add openh264 & x264 include path
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
347864152d sim codec: add dependence to Kconfig
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
61f79757f7 v4l2m2m/sim encoder: move hostencoder to x264encoder
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
7248ba0293 sim decoder: update CMakeLists.txt
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
shizhenghui
3675cfe585 v4l2m2m/sim decoder: rename hostdecoder to openh264dec
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-07-16 08:33:50 -03:00
Eren Terzioglu
0df037855a esp32[c3]: Add mcuboot build script for esp32c3-legacy 2024-07-16 10:30:56 +08:00
Eren Terzioglu
a9082e0882 esp32[s2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
c9f5ae5fa4 esp32[s3]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
024e95875a esp32: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
Eren Terzioglu
553b1f5f5e esp32[c3|c6|h2]: Add nuttx toolchain support on mcuboot 2024-07-16 10:30:56 +08:00
adriendesp
baf52268cc arch/xmc4: Added pwm driver 2024-07-15 16:14:55 -03:00
Peter van der Perk
622b6d234a s32k1xx: FlexIO I2C master driver 2024-07-15 10:06:55 -03:00
Raman Gopalan
ef271b8fe2 at32uc3a0: Initial work for SimpleMachines' Mizar32-A 2024-07-15 20:46:41 +08:00
Yanfeng Liu
8bdc975abb riscv/cmake: fix Toolchain.cmake issue
This fixes the following issue when configuring canmv230:master
with Ubuntu stock toolchain and cmake 3.22:

```
CMake Error at .../arch/risc-v/src/cmake/Toolchain.cmake:218 (if):
  if given arguments:
    "STREQUAL" "GNU_RVG"
  Unknown arguments specified
```

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-15 19:41:03 +08:00
hujun5
a4fece3450 spin_lock: inline spin_lock
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
2024-07-15 02:29:30 +08:00
zouboan
ae8ce535f3 arm64/arm64_boot.c: Fix exception caused by accesses to ICC_SRE_EL3 when GICv3 was not implemented 2024-07-15 02:26:40 +08:00
Huang Qi
e047ab9c70 riscv: Initial support for debug trigger module
Implement up_debugpoint_add/up_debugpoint_remove for riscv.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-14 20:32:19 +08:00
Eren Terzioglu
c15c0d1a78 esp32[h2]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
Eren Terzioglu
0f0c258fa2 esp32[c6]: Add MCUBoot support 2024-07-14 11:38:29 +08:00
zouboan
ea532cb11a arch/arm64: add initial support for ZYNQ MPSOC
arch/arm64: add initial support for ZYNQ MPSOC

arch/arm64: add initial support for ZYNQ MPSOC
2024-07-13 20:51:39 -03:00
Yanfeng Liu
211e2cd8b9 riscv/k230: revise canmv230:pnsh
This revises canm230:pnsh in a few ways:

- adjusting linker scripts structure,
- asserting PMP setting results,
- adjusting configs for both k230d and k230 devices.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-07-13 07:21:22 -03:00
Michal Lenc
5c48944e0b samv7: fix compile warning in PWM and UART drivers
The following warnings is fixed:

chip/sam_pwm.c:961:12: warning: unused variable 'regval' [-Wunused-variable]
  961 |   uint32_t regval;

chip/sam_serial.c: In function 'sam_dma_txavailable':
chip/sam_serial.c:2264:7: warning: unused variable 'rv' [-Wunused-variable]
 2264 |   int rv;

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-13 11:37:06 +02:00
simbit18
f12c4e05cc Fix Kconfig style
Remove spaces from Kconfig files
Add TABs
Replace help => ---help---
Remove extra TABs
2024-07-12 06:37:59 +08:00
chao an
d4024c8388 arch/armv8-r: update g_running_tasks before context switch
fix invalid running_task() in assertion logic

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-12 00:39:37 +08:00
simbit18
2f8560e838 tools/ci: enable avr32dev1 build
removed in the tools/ci/testlist/other.dat file the entries
 -avr32dev1:nsh
 -avr32dev1:ostest

avr32_bringup.c
Fix  Error: ./avr32_bringup.c:54:4: error: #warning "Not Implemented"

comment out directive '#warning'
/* #warning "Not Implemented" */

avr_doirq.c

fix avr32/avr_doirq.c:117: error: assignment discards qualifiers from pointer target type
  regs = g_current_regs; -> regs = (uint32_t *)g_current_regs;
2024-07-12 00:39:21 +08:00
chao an
95a9facf3a arch/armv8-r: new config to set SPIs Configuration to edge-triggered
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-11 15:35:41 +08:00
Henry Rovner
091372069c risc-v/bl808: Add SPI driver
This commit implements a driver for SPI0 and SPI1 on the BL808 and introduces an accompanying example configuration.
2024-07-11 11:32:24 +08:00
chao an
b191153cdc arch/armv8-r: fix typos in config
replace ARMV7R to ARMV8R

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-10 18:41:13 -03:00
Michal Lenc
a91d40e0e8 samv7: fix CAN FD configuration
Larger RX/TX buffers might be required for both FD and FD_BSW modes.
Default bit timing values are also changed since the original ones
did not provide correct results for default SAMv7 board clock selection
(150 MHz clock frequency). The current values provide correct bit timing
with sample point as close to 87.5 %.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Michal Lenc
e16ee4dba3 can: enhance bit timing ioctl to set both nominal and data bit timing
This adds field type to canioc_bittiming_s structure that allows
to set/obtain bit timing for both CAN CC and CAN FD.
CANIOC_GET_BITTIMING is now bidirectional: user specifies type field
and gets other fields from the controller.

The commit also updates current CAN FD capable controllers using the
ioctl. The type is not checked for classical CAN only controllers
and nominal bit timing is returned regardless of type value.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-10 11:33:03 -03:00
Eero Nurkkala
48cf91a7be arm64/imx9: ccm: add default clk init
This adds enablers for setting various clocks to some default
values. Also, this provides helpers to grant nonsecure access
to a number of clocks. Bootloader may utilize these to make
the system boot in a deterministic manner.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-07-09 21:14:11 -03:00
xuxingliang
848eca04ca arch/arm64: allow to use custom idle
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
xuxingliang
94387630c9 arch/arm64: remove not used idle trace
Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-07-09 19:36:48 +08:00
Lwazi Dube
b881868f19 arch/arm/sama5: Fix typos in ohci driver comments. 2024-07-09 09:20:13 +08:00
Huang Qi
d0210c1174 riscv_tcbinfo: Fix register ordering for PC
X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-08 21:13:25 +08:00
chao an
cef9addbbb sim/cmake: enable garbage collection of unused input sections
enable --gc-sections for linker
enable -ffunction-sections -fdata-sections for compiler

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-06 11:31:40 +08:00
chao an
9915b80e30 arch/sim: add custom data section support
The link script of NuttX Simulator is generated through compilation
options. This PR will support configure special data sections in
kconfig to meet the support of 3rd party applications.

we need to follow the syntax of linker script. In 3rd-party applications, some data will be labeled as section:

| a.c:
| struct task_s a __attribute__((section(".data.custom.taska")));
| b.c:
| struct task_s b __attribute__((section(".data.custom.taskb")));

Data of the same type struct can be placed in a fixed location to reduce the overhead caused by searching:

|   .data           :
|   {
|     _custom_data_table_start = .;
|     KEEP(*(.data.custom.*))
|     _custom_data_table_end = .;
|   }

Such section declare can be configured via Kconfig in the PR:

| CONFIG_SIM_CUSTOM_DATA_SECTION=" .data : { _custom_data_table_start = .; KEEP(*(.data.custom.*)) _custom_data_table_end = .; } "

Signed-off-by: chao an <anchao@lixiang.com>
2024-07-05 16:45:36 -03:00
Jukka Laitinen
b008653ac0 arch/arm64/src/imx9/imx9_lowputc.c: Fix an arithmetic sign error in divisor calculation
In the algorithm there is a subtraction (int - unsigned), which results (potentially overflowed)
unsigned.

Passing this to macro ABS and the assigning to int doesn't work ( unsigned is always >= 0 ).

Fix this by replacing (dangerous) ABS macro with stdlib's standard "int abs(int)"
and change the substraction to (int - int).

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-07-05 21:47:07 +08:00
Jukka Laitinen
31644ec0f5 arch/arm64/src/imx9: Add an mtd driver for NOR flash on FlexSPI interface
This is an initial FlexSPI SPI NOR MTD driver for IMX9

This supprts M25P SPI NOR on FlexSPI for now, and can later be extended to other
SPINOR devices if needed. The following configurations are needed to use this driver:
  CONFIG_IMX9_FLEXSPI_NOR=y
  CONFIG_MTD_M25P=y

In addition, board initialization logic needs to call the imx9_flexspi_nor_initialize
to receive a pointer to the mtd device.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Co-authored-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-07-05 21:46:47 +08:00
Jouni Ukkonen
31a6a4f5d0 imx9: Add flexspi support, ported from imxrt
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-07-05 21:46:47 +08:00
Henry Rovner
a83e7ced77 ox64: Add adc example config 2024-07-05 13:17:02 +08:00
Henry Rovner
8493273c2c risc-v/bl808: Add GPADC character driver
This commit implements a character driver for the general purpose ADC of the BL808, based on the hardware scanning functionality. The driver supports setting different conversion resolutions and the order of channels to be scanned via menuconfig.
2024-07-05 13:17:02 +08:00
Filipe Cavalcanti
0c63840b18 arch/risc-v: add support for capture driver on ESP32C6 and ESP32H2. 2024-07-04 18:24:50 -03:00
Daniel P. Carvalho
3e4a16d851 arch/arm/stm32: Fix EXTI lines definitions for STM32G47XX. 2024-07-04 18:23:51 -03:00
Michal Lenc
f1ef5daa92 samv7/sam_mcan.c: fix TSEG1, TSEG2 and SJW compile warnings for MCAN1
Following warnings were caused by incorrect naming of few defines.

chip/sam_mcan.c:415:7: warning: "MCAN1_NTSEG1" is not defined, evaluates to 0 [-Wundef]
  415 | #  if MCAN1_NTSEG1 > 63
      |       ^~~~~~~~~~~~
chip/sam_mcan.c:418:7: warning: "MCAN1_NTSEG2" is not defined, evaluates to 0 [-Wundef]
  418 | #  if MCAN1_NTSEG2 > 15
      |       ^~~~~~~~~~~~
chip/sam_mcan.c:421:7: warning: "MCAN1_NSJW" is not defined, evaluates to 0 [-Wundef]
  421 | #  if MCAN1_NSJW > 15

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2024-07-04 18:23:13 -03:00
Almir Okato
652f4f1fe1 esp32[s2|s3]: add volatile bitfields compilation flag
This compilation flag was added in the same way as done for esp32
in order to avoid unexpected behaviors when accessing registers
using struct bitfields.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-07-04 18:22:24 -03:00
Almir Okato
593dc946d1 esp32: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32 targets and removes the need
for running 'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-07-04 18:22:24 -03:00
Almir Okato
6ec690cbfc esp32[s2|s3]: move rom segments mapping to espressif common folder
Move and unify map_rom_segments function called when starting
Simple Boot and MCUboot compatible images.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-07-04 18:22:24 -03:00
Peter van der Perk
6b79aea0cf imxrt: Correctly update PLL, bit has to toggled instead of being set 2024-07-04 13:00:19 -03:00
buxiasen
c641148bc4 sim: make possible keep ubsan and bypass feature
sometimes ubsan work with asan trigger a mistake report, make it
possible to export library with ubsan, and bypass runtime feature.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-07-04 21:36:02 +08:00
nuttxs
8cd207e1b1 ESP32: emac initialization adding cpu id 2024-07-03 22:54:28 +08:00
Marco Casaroli
b8c1ce45e6 refactor(esp32-qemu-openeth): use lower half driver interface
This current driver does not handle well netpkts used in the
write buffers.

I learned about this document:

https://github.com/apache/nuttx/blob/master/Documentation/components/net/netdriver.rst

After I ported and contributed the original driver.

However from the document, I understand these types of drivers are
simpler to implement and I could simplify the driver and handle
correctly the TCP write buffers.
2024-07-03 08:52:14 -03:00
p-szafonimateusz
8682321d0c arch/x86_64: addrenv support
Add addrenv support for x86_64.
For now we support mapping on PT level, so PD, PDT and PML4 are static

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-03 17:40:53 +08:00
p-szafonimateusz
0200a48f72 arch/intel64/intel64_map_region.c: use MMU api to implement up_map_region
use new MMU api to implement up_map_region().

The new implementation support maping over 0xffffffff but requires CONFIG_MM_PGALLOC=y

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-03 17:40:53 +08:00
p-szafonimateusz
b1f3435d22 arch/intel64: add support for MM_PGALLOC
add support for MM_PGALLOC for x86_64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-03 17:40:53 +08:00
p-szafonimateusz
e0183927b4 arch/x86_64: add MMU interface
add MMU api for x86_64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-03 17:40:53 +08:00
p-szafonimateusz
53d112fa95 x86_64: add ELF support
add arch_elf64.c for x86_64, ported from sim/x86

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-03 17:40:53 +08:00
Daniel P. Carvalho
9f69652835 Added support for STM32G47XXX devices. 2024-07-03 08:49:16 +02:00
Daniel P. Carvalho
fa80408a06 arch/stm32: PLL clock is not available for HRTIM clock source on STM32G47XX devices (STM32F3XXX only). 2024-07-03 08:49:16 +02:00
Daniel P. Carvalho
c045558241 arch/arm/stm32: Added EXTI lines for STM32G47XX. 2024-07-03 08:49:16 +02:00
p-szafonimateusz
e6553eee5a libc/x86_64: port string functions from bionic
port optimized string functions for x86_64 from Bionic (BSD licensed)

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-02 23:59:18 +08:00
Masayuki Ishikawa
04c19bb1c9 Revert "irq: remove restore_critical_section in irq"
This reverts commit f6a9e91057.
2024-07-02 15:46:20 +08:00
hujun5
80fdf95790 tee: smp support
During the boot phase, when we transition from tee smp to ap smp, we can use a busy waitflag to wait for the completion of the initialization of ap's core0

test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-07-02 13:31:41 +08:00
hujun5
600368fbe2 smp: add busy wait flag
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-07-02 13:31:41 +08:00
hujun5
f6a9e91057 irq: remove restore_critical_section in irq
Only in the non-critical region, nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be restored

test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-07-02 03:00:57 +08:00
Marco Casaroli
f5de966471 fix(esp32-qemu-openeth): allocate buffers in internal memory
When the PSRAM is enabled, we should not allocate the TX/RX
buffers there, so we use kmm_calloc here, to make it into IRAM,
so the ethernet controller can read bytes from it.
2024-07-02 02:56:33 +08:00
p-szafonimateusz
bd73a915bd arch/x86_64: add support for FMA, AVX-2 and AVX-512
add support for FMA, AVX-2 and AVX-512 instruction sets for x86_64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-01 13:27:33 +08:00
p-szafonimateusz
2192d83200 arch/x86_64: add support for XSAVE/XRSTOR
Add support for XSAVE/XRSTOR to handle x86_64 procesor extended states.
Support for these instructions is required to support AVX instruction set

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-07-01 13:27:33 +08:00
p-szafonimateusz
66516918ce x86_64/irq.h: use 32bit operations in up_cpu_index()
Use 32bit operations for id field in intel64_cpu_s which is int type.

This fixes an error that appears when enabling some debug options:
  `Error: operand size mismatch for `movq'``

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-06-30 21:40:50 +08:00
xuxingliang
c6d712df0e sched: move nxsched_dumponexit() to task_exithook
So the tcb->group still exists to dump files.

Signed-off-by: xuxingliang <xuxingliang@xiaomi.com>
2024-06-30 17:30:42 +08:00
yinshengkai
5a31d52fd8 files: add files_dumplist api, replace dumponexit implementation
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-06-30 17:30:42 +08:00
p-szafonimateusz
8220b169f3 arch/intel64: add SMP support
modified various intel64 files to support SMP

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-06-29 22:37:48 +08:00
p-szafonimateusz
8d4681a190 arch/intel64: add support for AP cores boot
Intel64 can now boot application cores which is needed for SMP

IMPORTANT: CONFIG_BOARD_LOOPSPERMSEC must be properly configured,
otherwise AP boot sequence can fail due too short delays during the AP startup

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-06-29 22:37:48 +08:00
p-szafonimateusz
961ade88fe arch/intel64: add support for inter-processor signaling
Add support for inter-processor signaling in x86_64 based on up_trigger_irq() interface.
Preparations for SMP.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-06-29 12:57:37 +08:00
Huang Qi
c66b0866e8 riscv_exception.c: Add missing comma in exception reasons array 2024-06-28 17:00:11 -03:00
Yanfeng Liu
28eaa08cbc arch/riscv: fix PMP in sbi_start()
This fixes PMP setting for open everything before going S-mode, which
has been broken since pull/12398.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-28 21:30:53 +08:00
hujun5
13bbea0f1c arm64: inline up_cpu_index
reduce the time consumed by function call

test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-06-28 21:29:33 +08:00
p-szafonimateusz
c6170286ca arch/intel64: add cpu specific data and per-cpu interrupt stacks
Use GS base regsiter to store reference to CPU private data.
Then we can easily refer to private CPU data using the GS segment.

Required for SMP support.

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-06-28 09:40:32 -03:00
Yanfeng Liu
cd57bc16c7 riscv/pmp: add all region in NAPOT
This allows using 0 base and size to depict the whole region.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-06-28 17:54:46 +08:00
SPRESENSE
34426416e7 arch: cxd56xx: Add audio sources to CMakeLists.txt
Add audio source files to CMakeLists.txt.
2024-06-28 17:53:56 +08:00
SPRESENSE
b4d6e585c2 arch: cxd56xx: Add gnss source to CMakeLists.txt
Add a gnss source file to CMakeLists.txt.
2024-06-28 17:53:56 +08:00
Eren Terzioglu
dcea703bae esp32[c3|c6|h2]: Add GDMA support 2024-06-28 17:52:56 +08:00