Squashed commit of the following:
arch/arm/src/s32k1xx: Update peripheral input clocking for the way that things are done for the S32K1XX. Fix other misc. compilation/configuration issues.
arch/arm/src/s32k1xx: Clean up LPSPI and LPI2C naming for S32K1XX. Using S32K1XX clock functions to get peripheral input clock.
arch/arm/src/s32k1xx: Clone i.MXRT LPSPI and LPI2C support. i.MXRT uses the same IP as S32K1XX.
arch/arm/src/s32k1xx/s32k1xx_lowputc.c: Fix a typo that prevented LPUART1 from working.
arch/arm/src/s32k1xx/s32k1xx_periphclocks.c and related files: Fix yet another case of confusion between pre-decremented and non-decremented divider values. Enforce the rule that dividers are not decremented until the moment they are written into registers.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Fix another problem related to whether a divider is pre-decremented or not. The answer must be the divder values are never pre-decremented. They are decremented just before being written to hardware.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Clean up some bad conditional logic. Precedence of operators problem.
boards/arm/s32k1xx/s32k118evb: Add support for execution out of SRAM. This is helpful for bringup when you want to avoid putting a lethal image in FLASH.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h: Remove crystal frequency, it is not used.
arch/arm/src/s32k1xx/s32k1xx_wdog.h: Fix a typo in a register name.i
boards/arm/s32k1xx/s32k*evb/configs/nsh/defconfig: Create Motorola SREC output format.
boards/arm/s32k1xx/s32k118evb/include/board.h: Add LPUART0 pin disambiguation.
arch/arm/src/s32k1xx/hardware: Add pin mux definitions for S32K116, 118, 142, 144, 146, and 148.
arch/arm/src/s32k1xx/s32k1xx_pin.c and .h: Add support for PIDR register that disables a gneral purpose pin from acting as an input.
arch/arm/src/s32k1xx/s32k1xx_pin.c and .h: The device does not support slew rate controls or open drain (on all the pins). Only pins that are configured for a protocol that requires open-drain (e.g;, LPI2C, LPUART single-wire) will work in open-drain mode.
arch/arm/src/s32k1xx/: Add logic to look up the peripheral clock frequency. Fix baud calcuation logic in s32k1xx_lowputc.c: In no longer tries to enable clocking. That must be done with board logic. Now gets the peripheral functional clock frequency to determine the baud rate.
arch/arm/src/s32k1xx: Add peripheral feature arrays.
Finishes peripheral clock initialization:
arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c
arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c
Provide MCU-specific mapping of clock names to PCC control registers.
boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
Provides initial clocking for for the S32K118EVB
arch/arm/src/s32k1xx/s32k1xx_periphclocks.c: Add logic to initialize peripheral clocking.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Add SIM clock configuration.
stm32h7 RTC and friends support
* stm32h7:Removed f7 in file path
* stm32f7:Fix overwritten IRQ enabled
System boot order calls clock_initialize then up_initalize.
clock_initialize was setting up the alarm IRQ
up_initalize is initializing the NVIC.
This most likely worked in the past due to a bug in the
NVIC init code that failed to clear the Interrupt enables.
That was fixed in 510b0f7e arch/arm/src: Correct all ARMv7-M
architectures. Interrupts were not be disabled correctly
on power up.
* stm32h7:Ported over F7 RTC
* nucleo-h743zi:Add RTC
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Finishes the implementation of the core clock configuration logic.
arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h: Add SMC register definition header file.
arch/arm/src/s32k1xx: Bring in GPIO logic from Kinetis. Looks like the same IP.
serial single-wire: add possibility to specify pull-up instead of open drain
Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* Revert "Merged in yanqil-br/feature-multi_chan_pwm (pull request #973)"
This reverts commit aef0e0b538.
* arch/arm/src/{stm32/stm32f7/stm32h7/stm32l4}/stm32_pwm.c: configure multi-channel duty only if channel specified. This allows you to update duty cycle for a single channel
* nucleo-f303re/configs: add basic NSH configuration
* nucleo-f303re/configs/pwm: enable console on UART2 and set entry point to nsh_main
Approved-by: Gregory Nutt <gnutt@nuttx.org>
stm32f7: USART1_RXDMA is dependent on STM32F7_DMA2 not STM32F7_DMA1
Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva/Kconfig:
Remove EXPERIMENTAL dependency on TIVA_TIMER16_PWM.
arch/arm/src/tiva/common/tiva_timerlib.c:
Fix wrong 32/16-bit ifdef checks.
Add tiva_pwm16_sel_event() to choose GPTMCTL.TnEVENT value.
Implement tiva_pwm_mode16().
tiva_timer16_setinterval(): Fix wrong check for TIMER16_MODE_ONESHOT
and TIMER16_MODE_PERIODIC. Was comparing to config->cmn.mode
which can never have those values. This prevented interrupts being
enabled. Compare to timer->mode instead.
Add tiva_timer16pwm_setperiodduty() to set initial period, duty cycle,
and enable interrupts if requested in GPTM peripheral. Interrupts
are not enabled in NVIC until tiva_timer16_start() is called.
Add tiva_timer16pwm_setduty() to update duty cycle at any time.
arch/arm/src/tiva/hardware/lm/lm3s_timer.h,
arch/arm/src/tiva/hardware/lm/lm4f_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h:
Add missing defines; make surrounding defines consistent.
arch/arm/src/tiva/tiva_timer.h:
Add new TIMER_FLAG_* configuration flags to enable configuring the
16-bit PWM feature. Extend type of "flags" in tiva_timer32config_s
and tiva_timer16config_s from 8- to 32-bits to allow more flags.
If we are using the BASEPRI register to disable interrupts, then the answer is that we must disable ONLY the "normal interrupts". That is because we cannot disable SVCALL interrupts and we cannot permit SVCAll interrupts running at a higher priority than the high priority interrupts (otherwise, they will introduce jitter in the high priority interrupt response time.)
Hence, if you need to disable the high priority interrupt, you will have to disable the interrupt either at the peripheral that generates the interrupt or at the NVIC. Disabling global interrupts via the BASEPRI register cannot effect high priority interrupts.
arch/arm/src/tiva/common/tiva_timerlib.c:
* tiva_gptm_configure() and tiva_gptm_release(): Fix error: Was calling
tiva_emac_periphrdy() instead of tiva_gptm_periphrdy().
arch/arm/src/tiva/tiva_timer.h:
* Fix error in "abcde" description of bit flag defines.
kinetis:i2c transfer ensure correct result returned
kinetis_i2c_transfer released the mutex then fetched
the state, this resulted in returning the correct
results.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Move boards to boards folder
* boards: rename configs folder to boards
This is the proposed layout after the change:
boards: - folder containing board folders
<board>: - name of each board
drivers: - extra drivers specific for platform
include: - header files for the boars
scripts: - extra scripts specific for platform
src: - board specific code
tools: - extra tools specific for platform
<config>: - board specific configuration(s)
Note:
<xxx> names are dependent on platform
This is a logical change to aim to the arch layout but this is a
huge change it should be done in several steps to lower the risk.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Kconfig: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Makefile: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Makefile.*: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Make.defs: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .sh: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .mk: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .c & .h: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .bat: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Rationale: TM4C1294NC is ambiguous:
TM4C1294NCPDT is a 128-TQFP
TM4C1294NCZAD is a 212-NFBGA
The TM4C1294NC part currently supported by NuttX is the TM4C1294NCPDT used on the TI EK-TM4C1294XL "Connected LaunchPad" (see configs/tm4c1294-launchpad). To ensure the correct part is fully specified, this commit updates all TM4C1294NC identifiers to TM4C1294NCPDT.
Rename:
CONFIG_ARCH_CHIP_TM4C1294NC to CONFIG_ARCH_CHIP_TM4C1294NCPDT
ARCH_CHIP_TM4C1294NC to ARCH_CHIP_TM4C1294NCPDT
TM4C1294NC to TM4C1294NCPDT
Rationale: In terms of firmware programming, there is no functional difference between these parts:
TM4C123GH6PMI7
TM4C123GH6PMI7R
TM4C123GH6PMT7
TM4C123GH6PMT7R
From a programming standpoint, all of the above parts are TM4C123GH6PM, which means it doesn't make sense to differentiate between PM and PMI. (The PM means 64-LQFP. The I means temperature range -40C to +85C. It could be T meaning -40C to +105C. The R means it ships in Tape and Reel packaging as opposed to Tray.)
arch/arm/include/tiva/chip.h:
arch/arm/include/tiva/tm4c_irq.h:
arch/arm/src/tiva/hardware/lm/lm3s_flash.h:
arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h:
configs/tm4c123g-launchpad/README.txt:
configs/tm4c123g-launchpad/nsh/defconfig:
Rename: CONFIG_ARCH_CHIP_TM4C123GH6PMI to CONFIG_ARCH_CHIP_TM4C123GH6PM
arch/arm/src/tiva/Kconfig:
configs/Kconfig:
Rename: ARCH_CHIP_TM4C123GH6PMI to ARCH_CHIP_TM4C123GH6PM
arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h:
Rename: CONFIG_ARCH_CHIP_TM4C123GH6PMI to CONFIG_ARCH_CHIP_TM4C123GH6PM
Remove redundant Peripheral Base Addresses section. There were two identical copies, one for CONFIG_ARCH_CHIP_TM4C123GH6PMI and another for CONFIG_ARCH_CHIP_TM4C123GH6PM.
Testing of the WiFi is minimal so far but functionality is proven. I'm specifically not happy that the driver doesn't recover elegantly from a DMA data checksum failure, but that is an issue that can be dealt with in due course ... I'm trying to get the rest of the interfaces fleshed out and the hardware proven so it can go for pre-production build. I _think_ there's only Bluetooth and USB-device left to implement now.
