Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Completes review of configs/gapuino.
arch/risc-v/include/gap8/chip.h: Replace the moved chip.h header file with a dummy chip.h header file just to keep the system happy.
Move include/gap8/chip.h to src/gap8/chip.h. Internal details should not be exposed outside of arch/ and configs/. Review all headers files in src/gap8
Review of arch/risc-v/include.
Author: hhuysqt <hyq9606@126.com>
corrected author and email
Add app initialization, add signal support, cleanup irq context and configs
fix some warnings
gapuino initial port
GAP8 initial port
Adds definitions for IPPROTO_IPV6 socket options to netinet/in.h Adds missing fields to sockaddr_in6. Adds struct ipv6-mreq.
These changes all follow the opengroup standard for netinet/in.h
Approved-by: GregoryN <gnutt@nuttx.org>
Fixes logic in ipv6_input to handle more than ff02::/16 multicast addresses. Don't forward mcast packets if scope is not appropriate
Approved-by: GregoryN <gnutt@nuttx.org>
net/sixlowpan: Fixes bug in uncompress_addr handling of odd postfix.
This affected multicast compress/uncompress since it's the only logic that used an odd postfix. The odd byte needs to be handled first, not last.
Approved-by: GregoryN <gnutt@nuttx.org>
In addition to the problems that were previously identified there were a few other bits and pieces outstanding;
* Timing was dependent on CPU speed rather than absolute time
* End of transfer handling was a bit mixed up
* It's possible for data to still be in the FIFO (i.e. not have reached
the card) when a next write is requested, so we need to wait for that to
complete
* Interrupt Status could be carried over from one transfer episode to the
next, corrupting progress
* Multi-descriptor DMA writing simply wasn't implemented, but there were no
indications ... it just failed silently
Master imxrt
* imxrt:Fix typos bit# and names
* imxrt:wdog Registers are 16 Bits
* imxrt:wdog Update has to be within 255 clocks of unlock
* imxrt:clockconfig Fix comments
* imxrt1050-evk:board.h Fix comments
* imxrt:imxrt_ccm.h Define Mux Selects for board.h use
* imxrt:clockconfig Allow better control from board.h
1) Allows a board config clock setting to be defined
in terms of the /n values shown in Figure 18-2.
Clock Tree of the i.MX RT1050 Processor Reference
Manual, Rev. 1, 03/2018
2) Allows the clock multipelx selection to be made in
The board config.
* imxrt1050-evk:Define board clocking based on divisor and muxes
Approved-by: GregoryN <gnutt@nuttx.org>
* Clocks were wrongly configured - way too fast because there is no primary divider on LPC4330
This is fixed by means of changing the definitions in the board.h file. I've edited the one for the lpc4330-xplorer board because I'm actually working with Versiboard and don't want to contribute that config just yet while I've still got the drains up on it.
* The LPC43_SDMMC_DELAY register was not being set
I suspect, in the 'real world', it's possible to get away without setting this, but I've added a register definition, default value and register access macros into arch/arm/src/lpc43xx/chip/lpc43_scu.h and then used them in arch/arm/src/lpc43xx/lpc43_sdmmc.c.
* The LPC43_SDMMC_BLKSIZ and LPC43_SDMMC_BYTECNT registers had the wrong values.
The management have already implemented a rather nice block level interface for the stm32 so I've just re-used that to write to these registers as required. I'm slightly nervous that accessing the configuration registers (SCR being the prime example) which has a much smaller block size may not be being done in the right way but it does seem to work correctly, so let's assume it's all OK until someone tells me otherwise.
These fixes have been tested with DMA-based read/write on a LPC4330. Speed via nsh is pretty low but I'm assuming that's just a buffering/implementation issue for now.
