The qemu-rv use a small init code for M mode in kernel build.
It is hard-coding and is difficult to change. Due to the fact,
introduce a already mature SBI implement (e.g OpenSBI) to
replace existing code is a better choice.
This patch introduce some change for qemu-rv:
1. use SSTC to provide time interrupt in kernel build
2. remove uncessary M mode trap.
For simplicity, this patch does not add support for booting
nuttx for any core, but force boot core to start core 0 and
let core 0 do the initialization.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
SSTC extension allows nuttx to implement S-mode timer directly,
which is useful for starting at S-mode.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
As `up_get_intstackbase` supports per cpu stack base, fix
the report value with the cpu specific one.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
It is misleading to allocate stack from static array and heap,
make all stack allocated from heap area.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
according to manual:
The FPU is not affected by any security configuration.
Thus, it appears as not present in PERIPHID[n].PERM
register located in the SPU
This patch adds definitions to support user space device mappings
that allows devices like frame buffer to be accessible from user
space in kernel mode.
The are mainly two changes:
- in `mm/`:
added vm_map_region(), vm_unmap_region() for drivers to do
device mapping easily.
- in `arch/`:
extended ARCH_SHM_NPAGES as user-space mapping region size.
decoupled ARCH_SHM_MAXREGIONS from region size calculations and
limit its usage only for SysV shm purposes.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This patch adds a way to configure PLL frequencies. The configuration is
given by board logic.
These values should only be modified by the bootloader, but we don't have
that yet so the flag is never activated.
The frequency LUT idea is not necessary as the PLL output can be calculated
by the CPU. It is better to do this as the clocks are set by the SPL (2nd
stage program loader) which means the NuttX payload would not have access
to such a LUT anyhow.
The mask PLL_DIV_RDIV_MASK is also fixed, as that was simply wrong.
Also add call to imx9_clockconfig (although it does not do anything yet).
In some special chipsets, multiple CPUs may be bundled in one hardware
thread cluster, which results in hartid and cpuindex not being exactly
the same. The new option will decouple Scratch-based Per-CPU storage
with S-Mode to distinguish the real cpu index.
Signed-off-by: chao an <anchao@lixiang.com>
RISC-V provided fetch-and-op style atomic primitives as they scale
to highly parallel systems better than LR/SC or CAS. A simple
microarchitecture can implement AMOs using the LR/SC primitives,
provided the implementation can guarantee the AMO eventually
completes. More complex implementations might also implement AMOs
at memory controllers, and can optimize away fetching the original
value when the destination is x0.
Signed-off-by: chao an <anchao@lixiang.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Most of the functions used to describe the SoCs capabilities are
available for all Espressif's chips. This commit uses this set of
common functions and remove outdated functions that perform the
same operations in a chip level.
1. pm configuration demonstrates the use of power management present on the ESP32-S3.
2. You can use the pmconfig command to test the power management, for details look at
``Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst``
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
acpi_init() must be called early during boot, some system components may be
unavailable at this stage, so debug messages won't work
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This driver supports both eDMA3 and eDMA4 (also referred to as DMA0 / DMA1
in some contexts..)
The IP blocks are almost identical, with sufficiently minor differences
to use them via a unified driver. The price is a great amount of code
obfuscation in the hardware description layer.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.
flat and protected mode should be the same as before.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
rsdp memory may be not mapped when provided from multiboot2 header.
For some reason the previous code worked on some machines.
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
add simple ACPI parser for intel64.
For now RSDP signature can be found in BIOS legacy region or can be provided by multiboot2
Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
In file included from common/addrenv.h:33,
from common/riscv_initialstate.c:36:
common/riscv_initialstate.c: In function 'up_initial_state':
common/riscv_internal.h:136:16: warning: declaration of 'regval' shadows a previous local [-Wshadow]
136 | uintptr_t regval; \
| ^~~~~~
common/riscv_initialstate.c:74:12: note: in expansion of macro 'READ_CSR'
74 | regval = READ_CSR(CSR_VLENB);
| ^~~~~~~~
common/riscv_initialstate.c:63:13: note: shadowed declaration is here
63 | uintptr_t regval;
| ^~~~~~
Signed-off-by: chao an <anchao@lixiang.com>
LLVM supports (to various degrees) a number of experimental extensions.
All experimental extensions have experimental- as a prefix. There is
explicitly no compatibility promised between versions of the toolchain,
and regular users are strongly advised not to make use of experimental
extensions before they reach ratification.
Fix compile error:
riscv64-unknown-elf-clang: error: invalid arch name 'rv64gcv_zfh_zvfh', requires '-menable-experimental-extensions' for experimental extension 'zvfh'
Signed-off-by: chao an <anchao@lixiang.com>
- Add ARCH_KVMA_MAPPING to guard kernel mapping.
- Set dependency from MM_KMAP to ARCH_KVMA_MAPPING, as per commit
70de321de3.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros
are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable
should not be shifted right.
The SAMV7's qencoder driver now supports the GETINDEX ioctl call
which does not reset the internal Timer/Counter and returns
the current position, position of the last index and the number
of captured indexes to a struct qe_index_s pointer. Because the
SAMV7's timers are 16bit, the extension to 32 bits must be done.
Select CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX in the Kconfig to
enable this functionality.
This driver does not obey the instructions given in the ATSAMV7
2023 datasheet because the recommended trigger resets the internal
counter which is not desired. Instead, a capture into capture A
and capture B registers is used. This way if an event happens
(the rising edge of the index signal), the current counter's value
is captured.
Signed-off-by: Stepan Pressl <pressste@fel.cvut.cz>
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.
This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.
Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Currently Simple Boot image have fixed 2 ROM segments and
2 RAM segments, then the parsing iterator must stop when all
ROM segments are found.
Signed-off-by: Almir Okato <almir.okato@espressif.com>
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:
imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
54 | }
|
