Commit Graph

5708 Commits

Author SHA1 Message Date
Gregory Nutt
71c289ce4f Rename all architecture files of form xyz_internal.h to just xyz.h 2015-12-29 18:07:11 -06:00
Gregory Nutt
68cc2ecfd2 ATMEGA2560: Most cosmetic changes from review of pull request 2015-12-29 13:02:20 -06:00
Gregory Nutt
87a6662998 Merged in kloper/arch/atmega2560 (pull request #46)
Atmega2560
2015-12-29 12:20:09 -06:00
Dimitry Kloper
0b8a43abbb Merged nuttx/arch/master into atmega2560 2015-12-29 19:10:57 +02:00
Dimitry Kloper
3c0c90e07d Minor identation fix 2015-12-29 19:09:20 +02:00
Dimitry Kloper
3746305f12 AVR: Minor adapt to a differnt TIMER IRQ notions for Atmega2560 2015-12-29 19:08:13 +02:00
Dimitry Kloper
556954141e AVR: Add support for AVR chips with 24-bit Program Counter register
The main challenge is to change the context switch code to be aware of the
extra byte that is saved on stack during call and intterupt. This relates also
to the task startup and signal handling.
2015-12-29 19:01:06 +02:00
Dimitry Kloper
99aab135b2 AVR: Make setting of XDIV optional for platforms that support it
Put setting of XDIV into ifdef since not AVR platforms support it.
2015-12-29 18:56:12 +02:00
Dimitry Kloper
462307f4b7 AVR: Clear EIND on system start-up
For AVR chips (Atmega2560) Program Counter register larger than 16 bits
EIND represents the most significant byte that is used for EICALL and EIJMP
instructions.

Setting of EIND is normally managed by compiler, but I have seen a situation
when for first 64K flash segment compiler didn't set EINT explicitly. Thus
setting EIND at system startup makes sure we are safe.
2015-12-29 18:46:28 +02:00
Dimitry Kloper
9a4a06bf47 AVR: Explicitly disable interrupts as the first step of system init
Disabling interrupts at the very beginning of system init does not
make sense after reset since interrupts are disabled anyway. But
it is very convenient for debugging purposes, in situations when the
system misbehaves and ocassionally jumps to zero.
2015-12-29 18:35:36 +02:00
Dimitry Kloper
ff5e589f76 AVR: add support for TCGETS and TCSETS terminal controls
Sometimes I need UART to support binary data transfer, TCSETS/TCGETS allow
stwitching into binary mode.
2015-12-29 17:56:44 +02:00
Gregory Nutt
416e01bbfa TMS570: Add some placeholders for missing logic; fix some conditional compilation 2015-12-29 09:30:37 -06:00
Dimitry Kloper
d6f6e41a36 AVR: Fix linking error for AVR platforms that have no ARCH_HAVE_LEDS defined
Minor bug while working on Arduino Mega support. I didn't add support
for ARCH_HAVE_LEDS and have it undefined in .config. To my surprise compilation
failed since AVR code had a related function compiled in.
2015-12-29 17:26:11 +02:00
Dimitry Kloper
8f8b88f532 AVR: Fix resulting nuttx file name when EXEEXT is not empty
arch/avr/Makefile is adding extra EXEEXT to the
nuttix image file. This was not discovered since in most configurations
EXEEXT is empty string.
2015-12-29 17:19:30 +02:00
Gregory Nutt
7a0d6cd7ca TMS570: Fix an error introduced in last commit 2015-12-29 08:10:16 -06:00
Gregory Nutt
d9737f0645 TMS570: reset stack pointer before calling os_start 2015-12-29 07:56:22 -06:00
Gregory Nutt
e7d7036cb9 ARMv7-R: L2CC_VBASE->L2CC_BASE 2015-12-28 16:32:34 -06:00
Gregory Nutt
ae0e6b4096 ARMv7-R and TMS570: Re-orider some initialization logic. __start used to called arm_boot() which would return. Then __start would call os_start(). That won't work for the TMS570 if is does a destructive memory tested because the return information will be lost in the stack. Also comment a nuisance assertion. The assertion is probably correct but certainly a nuisance during initial testing 2015-12-28 16:15:33 -06:00
Gregory Nutt
00f70474bb TMS570: Power-up errcheck assertion is a headache 2015-12-28 08:30:03 -06:00
Dimitry Kloper
41bdcd16b8 Change notation of PCH and PCL registers into PC0 and PC1
This is for forthcoming Atmega2560 support. The Atmega2560 has 24-bit PC
thus, PCH and PCL would become PCH, PCM and PCL (M for Middle). The problem
that in this notation PCM is equivalent to former PCH. This makes compatable
porting kind of difficult, at least for my taste.

Instead PCH becomes PC0 and PCL becomes PC1 (think of the index as order of
bytes pushed to stack when call is performed, PC0 as MSB goes first, PC1
goes to stack second, and for 24-bit PC, PC2 as LDB goes last).
2015-12-28 00:46:24 +02:00
Gregory Nutt
c3758286d7 TMS570: Add ESM interrupt handler 2015-12-27 08:34:14 -06:00
Gregory Nutt
e0214f9d62 ARMv7-R: Remove some CONFIG_PAGING logic left over from ARMv7-A leverage 2015-12-27 08:32:53 -06:00
Gregory Nutt
e1b1f80237 TMS570: Add ESM initialization logic 2015-12-27 07:54:43 -06:00
Gregory Nutt
6d0650349a Add support for ARM big-endian toolchains with prefix armeb- 2015-12-26 18:13:01 -06:00
Dimitry Kloper
0c1294d332 Introduce a new Kconfig variant for Atmega2560 and add some basic stuff
Modify Kconfig to be aware of the new chip.
Add all the interrupt hanler constants and vectors where needed.
Move contsatnts from generic to specific headers when needed.
2015-12-27 01:47:35 +02:00
Gregory Nutt
46da8a07ef Costmetic changes from review of merge request 2015-12-26 16:39:51 -06:00
Gregory Nutt
21bdeac349 Merged in kloper/arch/avr_irq_bomb_fix (pull request #45)
AVR: Fix interrupt bombing during a context switch
2015-12-26 16:31:25 -06:00
Gregory Nutt
9bcf27d15b TMS570 is big-endian 2015-12-26 14:47:54 -06:00
Dimitry Kloper
0998876ef6 AVR: Fix interrupt bombing during a context switch
TCB_RESTORE macro has a problem when restoring Status Register
and returning from the function (in up_fullcontextrestore()) as non-atomic action.

If there is some frequently occurring interrupt, chances are that we will
enter the interrupt handler just before ret is called.
The handler may cause a context switch which, when unrolled, will
execute up_fullcontextrestore() function that employs TCB_RESTORE.
It will be interrupted again just before return, leaving part of context
switch content un-popped again, etc... Thus, chances are that the stack will
eventually blow.

Note that this is not some edge condition fix. This bug was discovered when
testing AVR with UART configured to work on 115200 baud rate.
2015-12-26 21:55:40 +02:00
Gregory Nutt
1f2d9c9174 TMS570: Does not have prioritized interrupts in the sense of other CPUs. Fix some compile errors when DEBUG is enabled 2015-12-26 12:26:57 -06:00
Gregory Nutt
d592b2824e TMS570: A little more selftest logic 2015-12-26 12:05:32 -06:00
Gregory Nutt
a27cd8e54e TMS570: Add the beginning of some selftest logic 2015-12-26 10:01:53 -06:00
Gregory Nutt
9c1b677bd5 TMS570: Clean up misc. build issues 2015-12-26 08:18:52 -06:00
Gregory Nutt
c58393cb4d TMS570: Add GIO drivrs and GIO interrupt support 2015-12-25 13:44:49 -06:00
Gregory Nutt
ccc6913383 TMS570: Add definitions to support GIO second level interrupts 2015-12-25 11:43:38 -06:00
Gregory Nutt
f539d331c5 TMS570: A few more GIO definitions 2015-12-25 11:30:08 -06:00
Gregory Nutt
0a936e7fa7 TMS570: More GIO definitions 2015-12-25 11:28:01 -06:00
Gregory Nutt
2563663a45 TMS570: Add GIO header file 2015-12-25 10:39:04 -06:00
Gregory Nutt
be99e773cf TMS570: Return serial status when a byte is read 2015-12-25 08:47:12 -06:00
Gregory Nutt
6b1f3da01a TMS570: Don't try building arm_fpuconfig.S for a Cortex-R4 2015-12-24 13:46:49 -06:00
Gregory Nutt
ea1fa2e938 TMS570: SCI serial driver is now included in the build and compiles without error 2015-12-24 13:37:42 -06:00
Gregory Nutt
90cfe8e23b TMS570: Initalize SCI interrupt handling logic 2015-12-24 12:35:22 -06:00
Gregory Nutt
af1504ec4a TMS570: Flesh out low-level serial console logic 2015-12-24 11:07:03 -06:00
Gregory Nutt
ba0f5467d0 A few more cosmetic changes 2015-12-24 07:38:17 -06:00
Gregory Nutt
376b35be39 Mostly cosmetic changes from review for conformance to coding standard 2015-12-24 07:35:19 -06:00
Gregory Nutt
f5340f0e2e Merged in pnb990/nuttx-kernel-arch (pull request #44)
Master
2015-12-24 07:14:14 -06:00
pnb
400d06e9ec fix capture bug 2015-12-24 12:26:39 +01:00
pnb
709c257a43 cosmetic 2015-12-24 09:45:02 +01:00
pnb
097b5820a1 Merge branch 'master' of bitbucket.org:pnb990/nuttx-kernel-arch 2015-12-24 09:42:48 +01:00
pnb
e22d8aea5d add oter timer 2015-12-24 09:42:33 +01:00