Once these messages are thrown during the system's bring-up, it is
advisable them to be output by the syslog considering the file
system initialization.
The SmartFS partition needs to be formatted before being mounted.
Otherwise, it would throw an error message. The error message now
contains a suggestion to format the partition when such an error
is detected.
Remove KEEP_ALIVE_HACK to avoid waking up the device periodly.
The workaround it's added by:
commit 6546fa39c7
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Tue Aug 12 11:12:00 2014 -0600
Tickless Stuff: Back out the risky timer operations when the ready-to-run
list is modified. That is unsafe. An ugly workaround is just to keep an
interval timer going all of the time with a minimum duration equal to the
timeslice interval.
But look like it doesn't needed anymore.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.
Major changes:
- boards/Kconfig: add new BOARD_K230_CANMV
- arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
select MMIO access width
New additions:
- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/: k230 SoC sources
- boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc
Note that only FLAT build works for canmv230 now.
This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.
Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.
The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.
So by design this change should be safe but RiscV ports should be checked.
"ostest" verification has been done for:
- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64
configuration generation and manual check of derived RV_MMIO_BITS has been
done for:
- star64/nsh
- arty_a7/nsh
- bl602evb/nsh
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
savedefconfig shouldn't overwrite the original defconfig, but only create a new
defconfig in the current directory. Otherwise, creating new configs based on
existing ones becomes irritating, because every time we use savedefconfig,
the original configuration is overwritten which is not the excepted behavior
The `xxx_ipv6multicast` function in each driver is not adapted to
multiple IPv6 addresses yet, and they're redundant, so try to take them
into common code.
Change:
1. Add MAC `g_ipv6_ethallnodes` and `g_ipv6_ethallrouters` in
`icmpv6_devinit` and call them in `netdev_register`
2. Add multicast MAC for Neighbor Solicitation when adding any IPv6
address, and remove them when IPv6 address is removed
3. Select `NET_MCASTGROUP` when `NET_ICMPv6` because now we need
`d_addmac` when we have ICMPv6
Note:
We want modules outside net stack to call functions like
`netdev_ipv6_add` and never touch the related MAC address, so these MAC
functions are added as internal functions to `net/netdev/netdev.h`
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
When CONFIG_NET_TCP_WRITE_BUFFERS is enabled, iobs are used for
both queuing data from application, and for assembling packets
for sending. If there is a system-wide shortage of iobs, it could
happen that there is not enough free space to form any packets
to send. The buffers allocated for TCP data also can't be released
until the packet is sent.
Normally this should be avoided by setting suitable values for
CONFIG_IOB_NBUFFERS and CONFIG_IOB_THROTTLE. The default values
are ok for light usage, but can run out when using multiple
simultaneous TCP streams.
Before this commit, iob shortage would cause TCP connections to
get stuck and eventually timeout. With this change, TCP stack
sends smaller packets, eventually freeing some buffers from the
write queue.
This PR adds support for PINE64 Ox64 64-bit RISC-V SBC, based on Bouffalo Lab BL808 SoC (T-Head C906 Core). Most of the code is derived from NuttX for Star64 JH7110. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
### Modified Files
`boards/Kconfig`: Added Ox64 board
### New Files in boards/risc-v/bl808/ox64
`src/bl808_appinit.c`: Startup Code
`include/board.h`: Ox64 Definitions
`include/board_memorymap.h`: Memory Map
`src/etc/init.d/rc.sysinit`, `rcS`: Startup Script
`src/.gitignore`: Ignore the tmp filesystem
`scripts/ld.script`: Linker Script
`scripts/Make.defs`: Ox64 Makefile
`src/Makefile`: Ox64 Makefile
`Kconfig`: Ox64 Config
`configs/nsh/defconfig`: Build Config for `ox64:nsh`
### Updated Documentation
`platforms/risc-v/bl808/index.rst`: New page for Bouffalo Lab BL808 SoC
`platforms/risc-v/bl808/boards/ox64/index.rst`: Building and booting NuttX for Ox64
`platforms/risc-v/jh7110/boards/star64/index.rst`: Fix typo
DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.
Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.
Test features can be used ad-hoc, they don't need to be supported by the
build.
and optimize the critical section usage
1.Remove the unnecessary critical section in ramlog_readnotify
2.Move the enter/leave critical section out of ramlog_pollnotify loop
3.Move the critical section of ramlog_addchar to caller
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1.Remove RAMLOG_OVERWRITE option and related code
2.Broadcast the readability to all reader and poller
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
-The qemu wifi fucntion only supports the STA mode and the following
operations:
wapi mode wlan0 2
wapi scan wlan0
wapi psk wlan0 password 3
wapi essid wlan0 wifi_name 1
wapi show wlan0
wapi disconnect wlan0
-Eanble the virtual wifi function with the MACRO `CONFIG_DRIVERS_WIFI_SIM`.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
As pointed out in #11322 there is a hardware design issue in RISC-V that
affects RV64 relocations. The problem is with how address bits are loaded
into registers via lui / auipc and sign extension.
If the hi20 relocation value happens to have its 32-bit sign bit set, i.e.
value is 0x80000000 (but not negative! i.e. negative in 64-bit format) the
relocation will fail, as the address is erroneously sign extended:
0x00000000_80000000 becomes 0xffffffff_80000000 which is not correct.
Also, make sure the correct opcode is used with PCREL_HI20, it expects
AUIPC (not LUI). The C compiler will never emit such code but when hand-
writing assembly code this can happen.
Previously ipv6 multi-address support decided packet source
address based on its destination. This doesn't work if NuttX
device has multiple addresses within same subnet.
Instead when a packet is a response to existing connection,
the source address should be based on the destination address
used in the received packet.
Refers to https://docs.oasis-open.org/virtio/virtio/v1.2/cs01/virtio-v1.2-cs01.html#x1-2230004
A driver SHOULD negotiate VIRTIO_NET_F_MAC if the device offers it.
If the driver negotiates the VIRTIO_NET_F_MAC feature, the driver MUST
set the physical address of the NIC to mac. Otherwise, it SHOULD use a
locally-administered MAC address.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
otherwise NUTTX_COMMON_DIR is empty if CONFIG_ARCH_BOARD_COMMON is set from menuconfig
Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.
Code size differences pre- and post:
Memory region Used Size Region Size %age Used
envm: 112064 B 112384 B 99.72%
Memory region Used Size Region Size %age Used
envm: 108952 B 112384 B 96.95%
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.
Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC
`include/bl808/chip.h`: BL808 Definitions
`include/bl808/irq.h`: External Interrupts
`src/bl808/chip.h`: Interrupt Stack Macro
`src/bl808/bl808_allocateheap.c`: Kernel Heap
`src/bl808/bl808_head.S`: Linux Header and Boot Code
`src/bl808/bl808_irq.c`: Configure Interrupts
`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts
`src/bl808/bl808_memorymap.h`: Memory Map
`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt
`src/bl808/bl808_pgalloc.c`: Page Allocator
`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver
`src/bl808/bl808_start.c`: Startup Code
`src/bl808/bl808_timerisr.c`: Timer Interrupt
`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address
`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses
`src/bl808/hardware/bl808_uart.h`: UART Register Addresses
`src/bl808/Kconfig`: BL808 Config
`src/bl808/Make.defs`: Makefile
Commit 8a63d29c removed `devif_iob_send` from `udp_sendto_buffered`
workflow, `devif_iob_send` drops too big packet. Now we still need a
place to check the packet length, otherwise a packet larger than MTU
may be sent to the net driver.
In case of similar problem happens somewhere else, this commit also
adds a check in `netdev_upperhalf`, and count these cases into
`NETDEV_TXERRORS`.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Busy waiting in w25qxxxjv_erase_sector() was without nxsig_usleep and
was causing the entire system to freeze for significant amount of time
as sector erase takes some time.
This commit adds nxsig_usleep into busy waiting to prevent system lock.
Sleep is set to sector erase time based on W25Q series datasheet.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
we can use uart to debug nuttx,like debugger:
1. read/write memory
2. Use watchpoint,breakpoint,single step.
use up_debugpoint api
3. Ctrl+c to stop, continue, or single step.
hold uart send and receive
4. register a panic event, when crash or assert/panic, we use uart to
debug.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
