Commit Graph

21310 Commits

Author SHA1 Message Date
Masayuki Ishikawa
a98650f609 arch: arm64: Remove unnecessary code in arm64_cpu_idle.S
Summary:
- I noticed that irq is enabled explicitly in arm64_cpu_idle.S
- The code is unnecessary since tasks, including the idle task,
  are created with irq enabled in up_initial_state()

Impact:
- Should be none

Testing:
- qemu-armv8a:netnsh_smp_hv with qemu-7.2.4

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-10-18 17:06:29 +08:00
zhangyuan21
48ca996ad7 arch: arm64 support smp function call
Add up_send_smp_call function to support smp function call.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-18 09:57:50 +08:00
Ville Juven
0e75e53cc8 mpfs_head.S: Simplify clearing PMP
Initially clear PMP for all harts, this fixes random warm reset issues.

Signed-off-by: Ville Juven <ville.juven@unikie.com>
2023-10-17 20:13:09 +08:00
Simon Filgis
882afc885e channel gain switching in aefc by ioctl
Update arch/arm/include/samv7/sam_afec.h

remove "offset may be uninitialized" warning

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/src/samv7/sam_afec.c

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/src/samv7/sam_afec.c

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

Update arch/arm/include/samv7/sam_afec.h

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>

remove blank line
2023-10-16 21:55:40 +08:00
Ville Juven
3f878d8100 mpfs_ethernet.c: Release tx descriptor and rx buffer properly
Instead of releasing rx descriptor twice and tx buffer twice.
2023-10-16 21:54:31 +08:00
Ville Juven
ee9e41f2dd mpfs_ethernet.c: Fix possible NULL de-reference
Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only
1 queue is currently set up for each, so the indices 1,2,3 are not valid
and should not be handled.
2023-10-16 21:54:31 +08:00
Ville Juven
64b6ac3d87 mpfs/mpfs_entrypoints.c: Fix potential R_RISCV_JAL linker error
Change bgtz t0, mpfs_opensbi_prepare_hart to tail-call to ensure there
will be no link time error due to the jump offset being too large.
2023-10-16 21:52:01 +08:00
zhangyuan21
21d9066c95 arm64: support up_coherent_dcache function
Before code is executed after being loaded into memory,
it is necessary to ensure the consistency of I and D cache.
The up_coherent_dcache function will flush the dache and
invalidate the icache to ensure cache consistency.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-16 16:08:23 +08:00
zhangyuan21
ca46cbb0bd arm64: target cpuid calculation error in arm64_gic_raise_sgi function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-16 16:08:04 +08:00
simbit18
2be45a3391 Update Fix more generic for platforms that do not have execinfo.h
Improve multiplatform code with __has_include.
2023-10-15 01:34:17 +08:00
TaiJuWu
1989749850 cpu_pause.c: fix typo
Signed-off-by: TaiJuWu <tjwu1217@gmail.com>
2023-10-14 00:26:31 -04:00
zhangyuan21
abfeafa876 arm64: XN should only be set when the attribute MT_EXECUTE_NEVER is set
Only when SCTLR_ELn.WXN is set to 1, regions that are writable at ELn
are treated as non-executable. Therefore, when SCTLR_ELn.WXN is set to
0, regions that are writable at ELn can be executed, so the writable
attribute cannot be used to restrict the executable attribute.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-13 22:48:13 +08:00
hujun5
cef8c598c7 arm64: Add support for FIQ interrupts
To compile arm64 NuttX, use the following command:
 ./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run,use the following command
 qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 16:56:24 -04:00
liqinhui
d27ca03b6c wifi/simdriver: Support the sim wifi.
Add the Sim WiFi function, which can provide the wifi operating on nuttx sim emulator,
  and support two modes that simulate wifi, HWSIM and RNC(real network card).

 - In the HWSIM mode, we simulates two wlan interfaces. The wlan0 is STA and
   the wlan1 is AP. The wlan0 can connect to the wlan1 in the nuttx simulator.
 - In the RNC mode, we can use the same wlan interface name on the nuttx simulator
   to control the connection behavior of the real wireless card.

Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2023-10-12 17:08:25 +08:00
hujun5
061be5f18e refine: move BIT Macro to nuttx/bits.h
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 14:52:56 +08:00
nuttxs
3d6e893215 esp32s3: fix the halt issue when esp32s3 wlan has high-speed
or long time data transmission.

The spin_lock in the wlan_recvframe() function that receives
RX data packets from the wireless network card and the critical
section lock in the iob_remove_queue() processing are nested,
which causes the interrupt to be disabled for a longer period
of time, resulting in a risk of deadlock.
2023-10-12 10:09:20 +08:00
Simon Piriou
c166c98e0c arch: x86_64: Fix idle stack assignment 2023-10-12 10:08:58 +08:00
simbit18
f22cff9b0b arch/arm/src/mx8mp/Kconfig: Fix Kconfig style
Remove extra TABs
Add comments
2023-10-12 01:38:53 +08:00
hujun5
66fa229fcc Fix some typos in comments
Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-11 08:14:49 +02:00
Lee Lup Yuen
6cad7e9582 arm, arm64, xtensa, libxx: Change sed -r to sed -E to support macOS
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):

```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```

This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.

This PR proposes to change `sed -r` to `sed -E` because:

- `sed -E` on macOS is equivalent to `sed -r` on Linux

- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual

- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
2023-10-10 11:36:32 +03:00
Philippe Leduc
f38cdb09b4 Add support for SPI through i.MX8MP ecspi module.
Configure SPI for Verdin evaluation board
2023-10-09 18:04:50 -04:00
Ville Juven
d199264dca kmm_map: Fix incorrect function name field 2023-10-09 18:59:43 +03:00
Ville Juven
3e8575c39e riscv-v/pgalloc.h: Return kernel vaddr for kernel RAM paddr
All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping
for kernel memory. Only interesting region should be kernel RAM, so omit
kernel ROM and don't allow re-mapping it.
2023-10-09 18:59:25 +03:00
Marco Casaroli
cba44cc9dc fix(esp32s3_i2c): i2c_clear_bus on for I2C_RESET
This function is only used now for I2C_RESET, so we wrap it with the
config macro.
2023-10-09 18:55:04 +03:00
Marco Casaroli
f25a382c1a feat(esp32s3_i2c): do not destuck every transaction
It looks like we do not need to send the 9 clock ticks whenever we reset
the FSM. We are already doing this in i2c_reset function if necessary.

This makes the i2c transfers much faster, for example the i2c(-tool) dev
scan feature.
2023-10-09 18:55:04 +03:00
Marco Casaroli
141dc1e3e7 fix(esp32s3_i2c): set regs order
It looks like we need to set this bit before the UPGATE, like we do on
the esp32c3 port.
2023-10-09 18:55:04 +03:00
Xiang Xiao
dfa0283d83 spinlock: Rename spin_islocked to spin_is_locked
align with Linux naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-10-06 20:03:19 -04:00
TaiJu Wu
1b843633e6 format: modify spin_lock_irqsave format
spin_lock_irqsave() should be spin_lock_irqsave(NULL)

Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
2023-10-06 20:00:04 -04:00
TaiJu Wu
ffba0d15a5 Feature: implement ticket spinlock
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp

Pass ostest

No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.

If they are equal, it means there is a task hold the lock or lock is
free.

Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>

Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
2023-10-07 01:38:37 +08:00
fengsi
7248b728bf UART needs to be disabled before changing setup 2023-10-06 20:49:26 +08:00
Ville Juven
7901ed0fe3 riscv_addrenv_utils.c: Determine page table flags by type of vaddr
Use kernel page table flags if the mapped virtual address is in kernel
space.
2023-10-05 20:38:35 +08:00
Tiago Medicci Serrano
6521bdfa1f esp32s3/ble: fix saving/restoring the interrupt status flags
Whenever we enter/leave a critical section, the interrupt status is
saved and, then, restored. However, for the ESP32-S3's BLE adapter,
entering/leaving a critical section is done on separate functions
that need to be registered as a callback.

The status flag was being saved as a global variable. However,
calling nested enter_critical_section would overwrite this global
variable that was storing the previous flag and, when leaving the
last critical section, the restored status would be different from
the one expected. The proposed solution for this issue is to create
a global array to store the interrupt status flags for nested calls.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
a71a3258b7 esp32s3/ble: enable the BLE interrupt during a SPI flash operation
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
0ddb64555a esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
86b118854e esp32s3/irq: Fix erroneous interrupt allocation for each CPU core
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32s3_setup_irq`.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
2e93882bcf esp32/ble: Fix task_create_wrapper CPU core ID passed as argument
The registered `task_create_wrapper` receives the `core_id`, but
the current implementation ignores this parameter while calling
`esp_task_create_pinned_to_core`. This commit fix this.
2023-10-05 00:37:55 +03:00
Eren Terzioglu
071fb18501 xtensa/esp32s2: add UART RS485 support 2023-10-04 10:18:45 +03:00
ThomasNS
2ffb72917d The character U+ff0c "," could be confused with the ASCII character U+002c ",", which is more common in source code. 2023-10-03 16:53:12 -04:00
Tiago Medicci Serrano
b8b0ae9238 esp32/irq: Fix erroneous interrupt allocation for each CPU core
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32_setup_irq`.
2023-10-03 16:51:49 -04:00
raiden00pl
d889b7362d arch: auto-select ARCH_PERF_EVENTS if some debug features enabled 2023-10-03 12:53:10 +08:00
raiden00pl
696d67870a arch/Kconfig: set ARCH_PERF_EVENTS default to n
This is a debugging feature so it should be disabled by default
2023-10-03 12:53:10 +08:00
raiden00pl
917fa624b9 arch/{all stm32 | all nordic | at32}: simplify the enable condition for up_perf_init 2023-10-03 12:53:10 +08:00
Carlos Sanchez
8e80d05fbb arch/arm/src/stm32h7/stm32_oneshot.c: Fix format warnings.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-10-02 16:41:13 -04:00
Carlos Sanchez
f3576a41f5 arch/arm/src/s32k1xx: Fix warnings in PWM code. 2023-10-02 23:36:37 +08:00
Carlos Sanchez
33cfd630ad arch/arm/src/s32k1xx: Fix LPUART inversion warnings & config. 2023-10-02 23:36:01 +08:00
raiden00pl
c93c0ecd81 samv7/adc: always increase initialization counter when adc_setup called 2023-10-02 23:34:24 +08:00
raiden00pl
cf4b8dbfa3 imxrt/adc: always increase initialization counter when adc_setup called 2023-10-02 23:34:24 +08:00
raiden00pl
b7fca7ff75 at32/adc: always increase initialization counter when adc_setup called 2023-10-02 23:34:24 +08:00
raiden00pl
577bdbf1fc stm32{f7}/adc: always increase initialization counter when adc_setup called 2023-10-02 23:34:24 +08:00
Ville Juven
8c6be8e1f3 riscv/addrenv: Fix the user VMA end address
The end address was off by 1, making it overflow to 0 (u32 value).
2023-09-29 22:34:40 +08:00