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75760a9fdb
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20480 Commits

Author SHA1 Message Date
wangming9
75760a9fdb arch/arm64: Adds custom chip option 
Signed-off-by: wangming9 <wangming9@xiaomi.com>
 2023-04-10 16:23:49 -03:00
raiden00pl
5e5fcd8076 fix copy-paste errors for d356ad633f 2023-04-10 03:21:36 -07:00
Petro Karashchenko
665a8e5b93 arch/arm/samv7: fix operation of TC8 and TC11 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-04-07 12:28:45 -03:00
Petro Karashchenko
4f3faded71 arch/arm/samv7: fix comment in freerun timer 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-04-07 12:28:45 -03:00
Gustavo Henrique Nihei
8e83379b84 risc-v/espressif: Initialize HR Timer where it is required 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-07 12:27:56 -03:00
Gustavo Henrique Nihei
ebe4ab8894 risc-v/espressif: Add support for RTC subsystem 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-07 12:27:56 -03:00
Tiago Medicci Serrano
b6e92fa16d esp32s3/wifi: call softAP callback when Wi-Fi driver TX is done 
In one of the previous code revision, the '#ifdef' for calling the
softAP callback was thrown away.
 2023-04-06 20:58:58 +03:00
Dong Heng
a51e102a41 xtensa/esp32: Make asprintf and lib_free corresponding 2023-04-06 20:57:19 +03:00
Tiago Medicci Serrano
00c3463426 arch/xtensa: Remove FAR qualifier for Xtensa-specific files 
This PR intends to remove all references to the FAR qualifier from
Xtensa files. FAR is defined as nothing on both architectures.
 2023-04-06 14:36:26 -03:00
Gustavo Henrique Nihei
38861f6154 risc-v/espressif: Use spinlock APIs for defining critical sections 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-06 14:35:36 -03:00
raiden00pl
d356ad633f {stm32,stm32f7,stm32h7,stm32l4,efm32}/otg: rasie an assertion if IN request is not possible to transfer 
Otherwise, a request will never be transferred and there is no
information to the user that something is wrong.
For example, when using default values for TXFIFO in HS mode,
USBMSC will never work because the maximum request len is 512B
which is lower than the default TXFIFO size for IN EP.
 2023-04-06 19:30:53 +03:00
Gustavo Henrique Nihei
ac746fd87f risc-v/espressif: Add support for Tickless mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-06 19:29:23 +03:00
raiden00pl
62ff3f484e {stm32f7,stm32h7,stm32l4}/sdmmc: callback support requires HPWORK 2023-04-06 18:10:59 +03:00
pengyiqiang
961b86642a sim_x11eventloop: fix X11 event accumulation 
sim_x11events should process all x11 events in each event loop,
otherwise it will cause events to accumulate in the queue and affect the interaction.

Signed-off-by: pengyiqiang <pengyiqiang@xiaomi.com>
 2023-04-06 10:24:17 -03:00
Masayuki Ishikawa
5e7d48f4b0 arch: k210: Fix k210 timer on QEMU 6.1 or later 
Summary:
- I noticed that 'sleep 1' on nsh took 10 seconds on QEMU-6.1,
  though the old version (e.g. QEMU-5.2) works correctly.
- I think we should implement PLL for the QEMU environment.
  However, this fix works as a tentative solution.

Impact:
- K210 on QEMU only

Tested
- Tested with QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2023-04-06 00:54:08 -07:00
Gustavo Henrique Nihei
8be8aab9bb risc-v/espressif: Panic if CPU interrupt allocation fails 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-05 16:52:07 -03:00
Gustavo Henrique Nihei
7aecd751f0 risc-v/espressif: Add support for Oneshot Timer 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-05 16:51:34 -03:00
Gustavo Henrique Nihei
31d68f2dd3 risc-v/espressif: Add support for Periodic Timers 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-05 16:51:34 -03:00
raiden00pl
1ace09cf10 stm32h7/otgdev: FS transceiver must be enabled if OTGFS enabled 2023-04-05 13:34:09 -03:00
Tiago Medicci Serrano
89b966a4f5 esp32/wifi: notify networking layer about the carrier status 2023-04-05 10:26:27 -03:00
Tiago Medicci Serrano
eb01b66978 esp32/wifi: fix typos, goto and macro definitions 2023-04-05 10:26:27 -03:00
Tiago Medicci Serrano
49d43a35b9 esp32/wifi: set Wi-Fi driver parameters only when needed 
This commit fixes #7857 and #7193 by saving Wi-Fi parameters and
set them at once, avoiding unknown behaviors of the Wi-Fi driver.

This commit also enables setting the auth of the STA/softAP modes
while connecting to/providing the wireless network.
 2023-04-05 10:26:27 -03:00
raiden00pl
83cdaeb593 stm32h7/otg: add support for external ULPI 2023-04-04 09:25:00 -07:00
raiden00pl
f89d2be99f stm32h7/rcc: OTGHS ULPI works only in VOS0 
This is not documented by ST at all but otherwise ULPI is dead.
 2023-04-04 09:25:00 -07:00
raiden00pl
d76b7c20ad stm32h7: update ULPI pins 2023-04-04 09:25:00 -07:00
yinshengkai
cafd3af160 arch/boards: fix stm32f411-mininum:nsh compilation failure after enabling IRQMONITOR 2023-04-03 09:05:21 +02:00
raiden00pl
71d7028c4a stm32h7/stm32_sdmmc.c: fix compilation 2023-04-02 17:20:17 -04:00
Huang Qi
7f27129896 tools: Move Rust relative settings to Rust.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2023-04-01 16:45:11 +03:00
Gustavo Henrique Nihei
ffef83c9a1 risc-v/espressif: Add High Resolution Timer driver 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-04-01 10:40:04 -03:00
GD32-MCU
6a799fef6c add littlefs support for gd32f450zk-eval board 2023-04-01 10:38:16 -03:00
Huang Qi
5d4e4b1919 tools/riscv: Map extensions to certain cpu model for LLVM based toolchain 
RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain.
For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c]
For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c]
So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by
all LLVM based toolchain.
Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td
These models can't cover all implementation of RISCV, but it's enough for most cases.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2023-03-31 16:55:15 -03:00
Gustavo Henrique Nihei
5081cef2c9 risc-v/espressif: Add Hardware RNG support 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-03-31 22:01:39 +03:00
Gustavo Henrique Nihei
cf90fa62b2 risc-v/espressif: Add support for System Reset 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-03-31 22:00:17 +03:00
Gustavo Henrique Nihei
c1efa8c85a risc-v/espressif: Fix include path for brownout.h 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-03-31 22:00:17 +03:00
raiden00pl
9bd865301c nrf52: add usb support 2023-03-30 09:28:55 -03:00
Ville Juven
fc44cbdbdb arch/risc-v: Set Supervisor User Memory (access) for idle process too 
This has been a long issue for me as it results in random crashes when
asynchronous events occur when the idle process is active.

The problem is that the kernel cannot access user memory, because the CPU
status prevents it.
 2023-03-29 10:53:09 -03:00
Stuart Ianna
01b0305ab5 risc-v: SV32 MMU support for qemu-rv. 2023-03-29 22:15:19 +09:00
Huang Qi
536739d2da tools: Export LLVM style arch info for non-c language 
Current Toolchain.defs set the compile flags directly, it's OK for
target specified gcc toolchain.

But some LLVM based toolchains (Rust/Zig etc) use single toolchain to handle all supported paltform.

In this patch, arch level Toolchain.defs export standard LLVM style arch flags, and let <Lang>.defs to map them into internal style,

This will simplify the intergration of non-c language.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2023-03-29 09:26:38 -03:00
raiden00pl
d23759d457 arch/nrf53: add tickless support 2023-03-28 19:43:35 -03:00
raiden00pl
f9f41bbd95 arch/nrf53: add RTC support 2023-03-28 19:43:35 -03:00
raiden00pl
bcecf2023f arch/nrf53: add GPIOTE support 2023-03-28 19:43:19 -03:00
raiden00pl
74b0e8c2c8 arch/nrf53: rename nrf53_gpioe.h to nrf53_gpiote.h 2023-03-28 19:43:19 -03:00
Gustavo Henrique Nihei
f462be5365 risc-v/espressif: Fix NULL-dereferencing in WDT interrupt handling 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-03-28 22:39:00 +03:00
Alan Carvalho de Assis
c5145257fe esp32: Add Ai-Thinker ESP32-A1S module 2023-03-28 20:58:36 +03:00
Gustavo Henrique Nihei
6647f194db risc-v/espressif: Update revision of esp-hal-3rdparty 
Small cleanup, no added features.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-03-28 14:43:40 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit 
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-03-27 12:35:04 +03:00
Petro Karashchenko
6c6a54b0c9 ld: fix warning reported by GCC 12 linker 
warning: nuttx has a LOAD segment with RWX permissions

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-03-27 12:38:28 +08:00
chao an
0eae218b49 arm/chip/sdio/muxbus: comment all undefined symbols 
comment all undefined symbols to avoid build break if CONFIG_SDIO_MUXBUS enabled

Signed-off-by: chao an <anchao@xiaomi.com>
 2023-03-26 13:04:48 -03:00
Lwazi Dube
21ffb4de72 boards/sama5d3-xplained: Make hot plugging more reliable. 2023-03-26 13:03:21 -03:00
Lucas Saavedra Vaz
6227cd4fd4 boards/xtensa/esp32s2-kaluga-1: Add touch pad support 2023-03-26 12:59:37 -03:00