Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
arch/arm/src/efm32/efm32_start.c:
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_NUTTX_KERNEL
efm32_userspace();
showprogress('E');
#endif
But there is no CONFIG_NUTTX_KERNEL configuration setting. Comparing this to other architectures it is clear this should be
#ifdef CONFIG_BUILD_PROTECTED
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Reason: xtensa svcall only have level-1 interrupt level.
Sush do not generate interrupt when up_irq_save.
Software int can generate interrupt when up_irq_save.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
`up_irqinitialize`. `esp32_cpuint_initialize` is not a good place as
it's also called from CPU1.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit fixes at least two issues.
* Fix a build with clang on linux
```
/usr/bin/ld: cannot open linker script file nuttx.ld: No such file or directory
clang: error: linker command failed with exit code 1 (use -v to see invocation)
```
* Restore symbol renaming for clang on linux
I guess it actually depends on the linker.
For now, use CONFIG_HOST_MACOS.
This fixed the following crash seen with sim/linux built with clang.
```
#135462 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
#135463 0x0000000000402aed in exit (status=1) at task/exit.c:103
#135464 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
#135465 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
#135466 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
#135467 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
#135468 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
#135469 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
#135470 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
#135471 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520
#135472 0x0000000000404a81 in nxtask_exithook (tcb=0x48f310 <g_idletcb>, status=1, nonblocking=0 '\000') at task/task_exithook.c:618
#135473 0x0000000000402aed in exit (status=1) at task/exit.c:103
#135474 0x0000000000475833 in host_abort (status=1) at sim/up_hostmisc.c:48
#135475 0x000000000040e6c6 in up_assert (filename=0x47b167 "semaphore/sem_wait.c", lineno=113) at sim/up_assert.c:126
#135476 0x000000000040850b in _assert (filename=0x47b167 "semaphore/sem_wait.c", linenum=113) at assert/lib_assert.c:36
#135477 0x0000000000403a40 in nxsem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:113
#135478 0x0000000000403b43 in sem_wait (sem=0x7fca38b1c2d0) at semaphore/sem_wait.c:271
#135479 0x000000000040aad3 in lib_stream_semtake (list=0x7fca38b1c2d0) at stdio/lib_libstream.c:159
#135480 0x000000000040a8e7 in lib_flushall (list=0x7fca38b1c2d0) at stdio/lib_libflushall.c:61
#135481 0x0000000000404c3c in nxtask_flushstreams (tcb=0x48f310 <g_idletcb>) at task/task_exithook.c:520
```
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.
This PR cleans up the logic so they're only listed once.
## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!
## Testing
CI will test all build
Summary:
- I noticed that pthread always crashes when started
if CONFIG_BUILD_KERNEL=y
- This commit fixes this issue
Impact:
- None
Testing:
- Tested with sabre-6quad:netknsh (not merged yet)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
State of problem:
- Some drivers that do not support write operations (does not
have write handler or ioctl do not perform any write actions)
are registered with write permissions
- Some drivers that do not support read operation (does not
have read handler or ioctl do not perform any read actions)
are registered with read permissions
- Some drivers are registered with execute permissions
Solution:
- Iterate code where register_driver() is used and change 'mode'
parameter to reflect the actual read/write operations executed
by a driver
- Remove execute permissions from 'mode' parameter
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Fix the CPU1 idle tasks stack corruption since the cpux's idle stack
is loaded from g_cpu_basestack (data section) before, but on this time
it maybe not ready since it is initialized by CPU0, and the value
from g_cpu_basestack is random.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
commit 328374f4658d11655f268f968f4c6c7a3942f320
changed the wait to use usleep. This killed the
write performace from the published values in the
datasheet of ~100 us to 2 mS per 256 bits. On
a 1000 per tick config. It can be 10 X worse
on the default 100 per tick config.
This changes uses up_udelay.
Architecture support for STMicroelectronics STMU585xx MCUs. This is
based on corresponding code for STM32L5, but has been considerably
adjusted. Tested with a B-U585I-IOT02A board and a simple NSH
configuration, but only running NuttX in the non-secure world with
TrustedFirmware-M.
Signed-off-by: Michael Jung <mijung@gmx.net>
This commit adds initial support for PWM driver to SAM MCU series.
Only general PWM on PWMH output is currently supported, complementary
output on PWML is not allowed. The current state of the driver also does
not support external triggering of other perihperals.
Multichannel option is supported. The functionality of the driver was
tested on an example pwm application and with a real time control system.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This change fix the regression that was introduced with
https://github.com/apache/incubator-nuttx/pull/4904
In case if D-Cache in configured in Write-Through mode there is
Cortex-M7 erata 1313001 that describes a situation when linefill
buffer or cache contains stale data. Even if progmem write loop
does not fully matches the description there is a possibility
to program stale data if there is no DMB instruction after each
write operation to progmem latch buffer.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
heap.
QEMU had a different ROM image that used the regions of PRO CPU for both
CPUs. This was causing crashes when running SMP mode as the heap was
being corrupted when the APP CPU starts.
QEMU is now loading the same image as the hardware chip and thus this
special case doesn't exist anymore.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
current implementation incorrectly update CURRENT_REGS to interrupt context if
trigger nested interrupt, (e.g, hard fault occurs during interrupt handling)
this would ambiguous for programs using CURRENT_REGS, this patch will prohibit
the update of CURRENT_REGS on nested interrupt handling
Signed-off-by: chao.an <anchao@xiaomi.com>
and removed two tcp_send_txnotify() calls from tcp_sendfile (they are not needed anymore).
As a result, the TX throughput of both the tcp_send_buffered and tcp_send_unbuffered
is significantly boosted in case of TUN/TAP network device.
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h
The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
- The function goes through every PMP entry and tests if an address
range from [base, base+size] has been configured for desired
access rights.
- If several PMP entries match the range and access rights, the
information is combined
- End result is either no access, a partial match was found, or a full
match was found. Details about the partial match are not provided.
The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW
This frees the PMP for other use, e.g. HART memory separation.
The page tables are statically allocated, 1 per level.
This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).
If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.
A more flexible solution for PMP configuration will follow.
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.
Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
Summary:
- I noticed that make export does not work with swama5d4-ek:knsh
- This commit fixes this issue.
- NOTE: apps/Makefile also needs to be updated.
Impact:
- CONFIG_BUILD_KERNEL=y only
Testing:
- Build (make and make export) with sama5d4-ek:knsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
- remove some unneeded includes
- tab/space fixes
- change DEBUGPANIC to PANIC in noreturn function, otherwise it compiles only in DEBUG builds
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
The following options need to be taken in account while determining
the proper hart_index2id -table:
CONFIG_MPFS_HART1_SBI
CONFIG_MPFS_HART1_SBI
CONFIG_MPFS_HART3_SBI
CONFIG_MPFS_HART4_SBI
Unused harts should be marked with -1. Hart0 is never used so it
stays at -1.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Commit 5d1a444812 replaced __attribute__
((unused)) with unused_code but two instances of __attribute__ ((used))
were also incorrectly replaced. Add used_code/used_data and used them
instead.
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Add two config flags for each hart for a bootloader nuttx:
CONFIG_MPFS_HARTx_SBI :
- select whether the hart boots via opensbi or not.
CONFIG_MPFS_HARTx_ENTRYPOINT :
- the target address to jump to, either directly from startup code or
from SBI if CONFIG_MPFS_HARTx_SBI is set
This allows building a nuttx based bootloader application, which can load
different applications/OSs for individual harts and jump to those
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Hart index to hart id table is used to track unused and used harts. This
table is useful when configuring only some of the harts for OpenSBI use.
Mpfs will always have the hart0 unused, so mark it with -1.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.
The driver is tested with mpfs only, but it should work with any riscv
implementation.
u-boot/kernel may use any uart, not just uart1, depending
on the device tree configuration. They will also reset the
corresponding uarts as well. It doesn't need to be done
here.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This drops the dependency to riscv_internal.h which ensures
less redefinition conflicts. OpenSBI declares some of the
variables again which are spread in many NuttX files.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.
Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
only on one hart, but the startup code executes on all harts and handles SW IRQs
Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
For Linux, we rename the section so that they are not invoked.
However, it doesn't work for macOS.
Notes:
* Renaming the sections (as the Linux version does) doesn't work
because the section is looked by its flags, not by its names.
* No convenient tools available to alter the relevant bit in
the section flags.
* The constructors are invoked before the program entry point.
As in _xtensa_syscall_handler, a3 was save and reused before
_xtensa_context_save, a3 save in _xtensa_context_save will generate
error.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
1. error in A3 push stack
2. when interrupt stack enable, push a12 is xtensa_irq_dispatch
parameter 1, instead of sp. As sp is interrupt stack address set by
`setintstack`, not the interruptee stack address
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
includes following parts:
add support of sparc in arch/Kconfig
add support of sparc in boards/Kconfig
add sparc dir in arch, add sparc dir in boards
add support of sparc in libs/libc/machine
modify all the coding style problem about saprc
Some SoC like bl602 require the exception entry 8 byte align, it should
be safe for other chips so we can apply it globally.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
In case of high TX network traffic, netdriver_loop() that reads data from netdev
was invoked via up_idle() only after high TX network traffic had stopped.
That resulted in massive delay and drop of TCP ACK packets and
any other packets from netdev (tun/tap device).
fw_start and fw_size were miscalculated. What was needed
was the pointed values of the offsets __mpfs_nuttx_start
and __mpfs_nuttx_end, not the values they had in place.
Also add the next_arg1 initialization.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
There are two issues that are addressed with this change:
- According to SAM E70/S70/V70/V71 Family datasheet the
timer counter channels are 16-bit so timer counter
value should be changed from uint32_t to uint16_t
- The interrupt handling for timer counter channels can
be simplified
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Also fix the wrong "dual-core" statement, since all ESP32-S2 chips are
composed of a single Xtensa LX7 core.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.
Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
It can provide better auto complete experience for modern code editor,
since they use clang/gcc based parser to analyze code but lacks some
target dependent info such as __LP64__ for riscv64.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
1. Fix the issue that Wi-Fi can't connect to some special routers occasionally.
2. Update Wi-Fi driver code to fix issue of failure to send pkt.
3. Replace software random with hardware random
commit 2889315c20 added support for pwm
but didn't read the channel numbers provided by user-space. They should
be, otherwise it's not possible to start a sub-set of channels that are
not the first "n" channels.
commit 7354ab187e added an option to break
the loops when using multiple PWM channels to arm pwm drivers. This adds
the same support to the risc-v pwm drivers.
The source directory contents of the OpenSBI directory lib/sbi may be
listed with a one-line wildcard. This makes the Make.defs file look
simpler. The rest of the files need to be picked one at a time.
Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.
OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.
OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.
Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:
opensbi_reserved: opensbi@80000000 {
reg = <0x80000000 0x200000>;
label = "opensbi-reserved";
};
The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
For FAT the same buffer is used for read and writes, there
is a possibility a cache line is dirty. But the fs is
not dirty and will not write the sector to disk. This can
be seen https://github.com/PX4/NuttX/pull/175
When the system is busy that cache line can be evicted after the
RX DMA has completed and overwrite the data in memory. The solution
is to invalidate before the DMA to prevent an evection causing an
overwite, and after the DMA it to insure coherency.
According to Make documentation:
- "Commas and unmatched parentheses or braces cannot appear in the text
of an argument as written";
- "Leading spaces cannot appear in the text of the first argument as
written".
Although in the current state it was not resulting in parsing issues, it
is better to fix it.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Current samv7 platform does not define SoC memories sizes. This define
both internal flash and sram memories sizes and update all defconfig
files.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
When it was in slow speed mode (by default), the output SDMMC_CK clock rise and
fall times were about 13 ns each, that were very slow and
prevented some SDIO devices from working.
This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.
The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.
The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c
Impact:
- None
Testing:
- Tested with lc823450-xgevk:bt
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2.fix some files to fix compile warning
3.remove blueteeth header files, which are not used in nuttx core.
4.fix configs and add lost files
5.update defconfig, remove useless items
6.fix compile warning for nuttx phyplus
7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder
8.fix file format check error on phyplus source code
9.fix phyplus kconfig param error
10.update configure file for nuttx
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.
DMA is inspired by SAMA5 driver and also uses ping pong buffers.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
we have many different hostfs implementation now, so it's better
to select the implementation explicitly, just like what we have
done for arm(FS_HOSTFS vs. ARM_SEMIHOSTING_HOSTFS).
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The FAT was not coherent. Resulting in a write failed
with errno:28 No space left on device.
It is unclear how the memory is acesses prior to the DMA
completion. But this restructuring ensures the data
is coherent.
This issue was not detected on the stm32h7
