Commit Graph

21 Commits

Author SHA1 Message Date
Abdelatif Guettouche
ea0dc8c1d2 arch/risc-v: up_allocate_heap is already declared in nuttx/arch.h
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-13 19:07:02 -03:00
Abdelatif Guettouche
44ada05549 arch/risc-v: Internal functions should be prefixed with riscv_ not up_
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-03-13 19:07:02 -03:00
Gustavo Henrique Nihei
330eff36d7 sourcefiles: Fix relative path in file header 2021-03-09 23:18:28 +08:00
hotislandn
30cb7d3983 arch:rv32:up_sigdeliver missing fpu contexts.
Signed-off-by: hotislandn <hotislandn@hotmail.com>
2021-02-24 23:42:18 -08:00
David Jablonski
41bddc8461 litex: fix mtime and mtimecmp register address 2021-02-13 15:24:28 -08:00
David Jablonski
11167857c3 litex: nsh working 2021-02-13 15:24:28 -08:00
Masayuki Ishikawa
d87f350831 arch, boards, drivers, include, sched, wireless: Change spinlock APIs.
Summary:
- This commit changes spinlock APIs (spin_lock_irqsave/spin_unlock_irqrestore)
- In the previous implementation, the global spinlock (i.e. g_irq_spin) was used.
- This commit allows to use caller specific spinlock but also supports to use
  g_irq_spin for backword compatibility (In this case, NULL must be specified)

Impact:
- None

Testing:
- Tested with the following configurations
- spresnse:wifi, spresense:wifi_smp
- esp32-devkitc:smp (QEMU), sabre6-quad:smp (QEMU)
- maxi-bit:smp (QEMU), sim:smp
- stm32f4discovery:wifi

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2021-02-07 21:28:56 -08:00
Abdelatif Guettouche
5447f28742 riscv: Remove the nx_start prototype from riscv_internal.h
This function is already declared in include/nuttx/init.h include this
file instead.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-02 17:48:40 -03:00
Abdelatif Guettouche
37b93bd498 arch/risc-v: Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1.
Don't declare riscv_addregion if CONFIG_MM_REGIONS is < 1, so we won't
have to provide a dummy stub for every chip.
Also rename the function from up_addregion to riscv_addregion since it's
not exported outside the arch directory.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-02-01 18:45:25 -08:00
Xiang Xiao
41d576f62b arch/riscv: Reuse the common up_schedule_sigaction implementation
to avoid the code duplication

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-12-20 20:26:27 -08:00
John Bampton
ba12c6c0cf Fix spelling 2020-12-12 19:18:08 +01:00
Huang Qi
4078548ae3 risc-v: Introduce basic setjmp support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2020-12-04 09:40:07 -03:00
YAMAMOTO Takashi
67ea358f96 arch/risc-v/src/litex/litex_schedulesigaction.c: Fix syslog formats 2020-11-24 22:31:33 -08:00
YAMAMOTO Takashi
316ca6cd86 arch/risc-v/src/litex/litex_serial.c: Fix a type mismatch 2020-11-16 08:29:00 -08:00
Juha Niskanen
d65acc6db4 arch: serial: fix typos and run nxstyle
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
2020-10-31 15:39:50 +01:00
Yoshinori Sugino
3de85be15a arch/risc-v/src: Branch to up_sigdeliver() with interrupts disabled
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
2020-09-28 22:41:46 -07:00
Yoshinori Sugino
698008d1e5 Fix typos 2020-09-28 13:54:43 +08:00
Ouss4
06ca12e6b9 arch/: Trivial typos, mostly "their is" to "there is" 2020-09-09 14:09:43 -04:00
Ouss4
21302fcdae arch/risc-v/src: Rename files starting by up_ to risc_ to conform to the
naming standard.
2020-04-30 20:48:32 -06:00
Nathan Hartman
9b86305ad3 Fix copy/paste typo in various Kconfigs 2020-04-14 22:42:21 +01:00
aenrbes
d450f5ce77
Add support for Litex VexRiscV. 2020-03-21 06:01:56 +00:00