Gregory Nutt
783bab6c82
Costmetic changes from review of last PR
2016-05-25 18:04:39 -06:00
Gregory Nutt
0d2698a710
Merged in ziggurat29/nuttx/stm32l4_i2c_lcd_mjkdz_001 (pull request #30 )
...
get I2C working for STM32L4
2016-05-25 17:58:19 -06:00
Gregory Nutt
3603dc6218
1-wire: Initialization/uninitialization functions are not use MCU-independent up_ naming. Should use STM32-specific stm32_ naming. These are not globally accessible but only accessible from STM32 board logic.
2016-05-25 17:56:47 -06:00
ziggurat29
003c2c737a
get I2C working. some more work regarding clocking computation is needed, as is some inhertited 'todo's from the basis code. but it does work with the devices tested so far.
2016-05-25 18:43:37 -05:00
Paul A. Patience
d31aefe4ef
STM32 CAN: Add support for both RX FIFOs
2016-05-25 16:11:18 -04:00
Gregory Nutt
add152bf24
Update README
2016-05-25 14:07:59 -06:00
Gregory Nutt
78e08bbeea
Purely cosmetic change from review of last PR
2016-05-25 13:29:01 -06:00
Gregory Nutt
fafc56ae80
Merged in ziggurat29/nuttx/stm32l4_i2c_lcd_mjkdz_001 (pull request #28 )
...
complete logic in 'create stack' and 'use stack' to support stack coloration. Fix some booboos breaking compatibility with TLS in libc.
2016-05-25 13:22:03 -06:00
Gregory Nutt
4afc4964ed
SAM34 TWI: Missing semicolon
2016-05-25 13:05:03 -06:00
Gregory Nutt
4a63a7760a
STM32: Hook 1-Wire driver into the build system
2016-05-25 12:31:32 -06:00
Gregory Nutt
9ec104834a
Remove CONFIG_USARTn_ISUART
2016-05-25 11:21:48 -06:00
Gregory Nutt
c089a2f241
Rename CONFIG_ARCH_HAVE_OTHER_UART to CONFIG_OTHER_UART_SERIALDRIVER
2016-05-25 10:48:33 -06:00
Gregory Nutt
e2e6ce3f1b
Rename CONFIG_ARCH_HAVE_SCIn to CONFIG_SCIn_SERIALDRIVER
2016-05-25 10:46:55 -06:00
Gregory Nutt
2a87741e72
Rename CONFIG_ARCH_HAVE_UARTn to CONFIG_UARTn_SERIALDRIVER
2016-05-25 10:45:01 -06:00
Gregory Nutt
249a2e48e5
Rename CONFIG_ARCH_HAVE_USARTn to CONFIG_USARTn_SERIALDRIVER
2016-05-25 10:39:23 -06:00
ziggurat29
05d2036334
complete logic in 'create stack' and 'use stack' to support stack coloration. Fix some booboos breaking compatibility with TLS in libc.
2016-05-25 10:37:38 -05:00
Aleksandr Vyhovanec
52c6cb1799
Fix typographical naming error in STM32 U[S]ART bit defintiions.
2016-05-25 09:04:03 -06:00
Aleksandr Vyhovanec
9a2002a302
1-wire driver based on U[S]ART in single-wire, half-duplex mode.
2016-05-25 08:59:47 -06:00
Frank Benkert
04223a9618
SAMV7: USBHS: Remove disabling of whole usb on suspend
...
This fix removes the disabling of the whole USB peripheral on suspend
interrupt. Its enough to freeze the clock instead.
When disabling the whole peripheral, the next wakeup-interrupt comes
up with an disabled clocking. The unfreeze clock has no effect, because
the master clock is disabled. This makes all registers, including the
IDR unwriteable and the IRQ falls in an endless loop blocking the whole
system.
Furthermore the disabling of the peripheral clock prevents hotplugging
or reconnecting the USB.
2016-05-25 07:20:48 -06:00
Gregory Nutt
317bf064a8
i.MX6: Clean up some initializers
2016-05-24 07:44:36 -06:00
Alexander Vasiljev
ad6f37edfa
Adds definitions for the LPC4337jet100 chip.
2016-05-24 07:03:50 -06:00
Gregory Nutt
3a8ff78f87
Restore PR. I have no idea where it went.
2016-05-23 17:45:15 -06:00
Gregory Nutt
e929066042
Fix an error in the last commit
2016-05-23 17:11:36 -06:00
David Sidrane
c41e6d823a
Add the up_systemreset interface to the samv7 arch. The approach is slightly different in that: 1) It enables ARCH_HAVE_RESET and allows the user to set if, and for how long, to drive External nRST signal. It also does not contain a default board_reset, as that really should be done in the config's src if CONFIG_BOARDCTL_RESET is defined.
2016-05-23 17:05:02 -06:00
David Sidrane
fca329945b
This patch ensures that the TWIHS (i2c) hw get's its clock set when the sequence of
...
sam_i2cbus_initialize
sam_i2cbus_uninitialize
sam_i2cbus_initialize
Or twi_reset is called.
I found this a while back in the stm32 family, so there may be more arch-es with this sort of bug. I suppose any driver that has the notion of "do not set the freq if it is already set" could be suspect.
2016-05-23 13:38:34 -06:00
Alexander Vasiljev
b43fcd6f99
LPC43xx: Add AES support.
2016-05-23 08:03:32 -06:00
Gregory Nutt
80d0b2736e
Reorder some logic: (1) set initial CPU IDLE task regsters AFTER allocating stack, (2) invalidate cache in CPU start-up BEFORE handling first interrupt.
2016-05-22 15:01:49 -06:00
Gregory Nutt
e47714322e
Merged in K-man23/nuttx/stm32f411e-disco (pull request #25 )
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Add basic configuration for stm32f411e-disco board with STM32F411VE chip
2016-05-20 17:54:07 -06:00
Konstantin Berezenko
a2253cdd3e
Add basic configuration for stm32f411e-disco board with STM32F411VE chip
2016-05-20 16:38:25 -07:00
Gregory Nutt
356692d70e
SMP: Need to enable FPU on other CPUs as well
2016-05-20 13:35:58 -06:00
Gregory Nutt
07acd5327a
SMP: Clean CPU0 D-Cache before starting new CPU; Invalidate D-Cache when new CPU started.
2016-05-20 12:39:02 -06:00
David Sidrane
916153fb75
Fix build if the config is not updated
2016-05-19 12:44:58 -10:00
Gregory Nutt
e27e87a957
Backing out part of last commit
2016-05-19 15:46:07 -06:00
David Sidrane
8fac871cc9
Adds a JTAG config and ERASE config to Kconfig to set the CCFG_SYSIO SYSIO Pins
...
• SYSIO4: PB4 or TDI Assignment
0: TDI function selected.
1: PB4 function selected.
• SYSIO5: PB5 or TDO/TRACESWO Assignment
0: TDO/TRACESWO function selected.
1: PB5 function selected.
• SYSIO6: PB6 or TMS/SWDIO Assignment
0: TMS/SWDIO function selected.
1: PB6 function selected.
• SYSIO7: PB7 or TCK/SWCLK Assignment
0: TCK/SWCLK function selected.
1: PB7 function selected.
• SYSIO12: PB12 or ERASE Assignment
0: ERASE function selected.
1: PB12 function selected.
The thing I did not add is warning or compilation failure, (to save the next guy the hassle), at ALL the driver points that uses the these pins.
I did remove this
/* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4
* instead of TDI
*/
uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO);
sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4;
putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO);
in sam_lowputc.c in favor of an #error - because the default is an input TDI and driving it blindly to an output TXD1, would be a contention.
2016-05-19 14:33:54 -06:00
Gregory Nutt
7f7d4e664c
Completely trivial changes from review of last PR
2016-05-19 14:09:00 -06:00
Sebastien Lorquet
ef66f641e9
small fix left from stm32
2016-05-19 21:57:59 +02:00
Sebastien Lorquet
6642898ee4
Merge branch 'master' into can
2016-05-19 21:49:31 +02:00
Sebastien Lorquet
8aae953f67
CAN support for STM32L4
2016-05-19 19:13:04 +02:00
Gregory Nutt
c364faeefc
SAM WDT: Rename up_wdginitialize() functions to something more appropriate for the internal OS interface.
2016-05-18 19:47:48 -06:00
Gregory Nutt
5d574549bd
stm32f103-minimum: Add schematic; remove unused watchdog driver logic
2016-05-18 15:37:42 -06:00
Gregory Nutt
f454b38d6e
ARMv7-A SMP: Allow CONFIG_SMP_NCPUS=1 for testing purposes
2016-05-18 09:17:02 -06:00
Gregory Nutt
72de45b7cf
Merged in david_s5/nuttx/upstream_to_greg (pull request #21 )
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Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build
2016-05-17 18:09:23 -06:00
David Sidrane
f444f061d6
Fixed Break changes needed CONFIG_SERIAL_TERMIOS to build
2016-05-17 14:04:51 -10:00
Gregory Nutt
5fc619eb1b
Changes from review of last PR
2016-05-17 17:39:27 -06:00
Gregory Nutt
4aeb06a79d
Merged in david_s5/nuttx/upstream_to_greg (pull request #20 )
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Upstream_to_greg
2016-05-17 17:30:45 -06:00
David Sidrane
bef5552eba
Support BSD compatible breaks on stm32fl4 U[S]ART
2016-05-17 13:09:34 -10:00
David Sidrane
3ffe7c378f
Support BSD compatible breaks on stm32f7 U[S]ART
2016-05-17 13:09:34 -10:00
David Sidrane
b11f49e7f1
Support BSD compatible breaks on stm32 U[S]ART
2016-05-17 13:09:34 -10:00
David Sidrane
55d8b0e277
Use the correct register and bit to send an STM32 non-bsd compatible break
2016-05-17 07:55:33 -10:00
Gregory Nutt
fb484a581f
All GCC final arch/*/src/Makefiles: Allow --start-group and --end-group to be redefined for the case where GCC is used to link (instead of LD). Suggested by Paul Alexander Patience.
2016-05-17 10:43:15 -06:00