Gregory Nutt
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51be83aa3a
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ARM: Fix missing header file. Update comments in all *_irq.c files.
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2016-03-09 15:08:58 -06:00 |
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Gregory Nutt
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4d4f54a789
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Rename current_regs to g_current_regs; For ARM, g_current_regs needs to be an array to support multiple CPUs
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2016-03-09 13:41:48 -06:00 |
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Gregory Nutt
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666cc280f4
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Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable()
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2016-02-14 16:54:09 -06:00 |
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Gregory Nutt
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83bc1c97c3
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Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
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2016-02-14 16:11:25 -06:00 |
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Gregory Nutt
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70e502adb0
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Replace irqsave() with enter_critical_section(); replace irqrestore() with leave_critical_section()
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2016-02-13 19:11:09 -06:00 |
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Gregory Nutt
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dfec6a0dd0
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Rename CONFIG_ARMV7M_MPU to CONFIG_ARM_MPU so that we can reuse the configuration settings for the ARMV7R MPU
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2015-12-14 13:56:21 -06:00 |
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Paul A. Patience
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52454cf79b
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Fix typo
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2015-11-11 13:06:15 -05:00 |
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Gregory Nutt
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beb060d422
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Yet more spacing issues
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2015-10-07 20:24:19 -06:00 |
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Gregory Nutt
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b6638315a4
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Correct some spacing issues
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2015-10-07 11:39:06 -06:00 |
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Gregory Nutt
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3fdd914203
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Costmetic fixes to C coding style
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2015-10-05 17:13:53 -06:00 |
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Gregory Nutt
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da6c5aabdf
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All ARMV7-M IRQ setup: Always set the NVIC vector table address. This is needed in cases where the code is running with a bootload and when the code is running from RAM. It is also needed by the logic of up_ramvec_initialize() which gets the vector base address from the NVIC. Suggested by Pavel Pisa
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2015-08-21 08:42:24 -06:00 |
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Gregory Nutt
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b1cecdd3ea
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SAMV7: Add interrupt-related logic
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2015-03-07 11:16:44 -06:00 |
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Gregory Nutt
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6455f60c60
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Remove os_internal.h it has been replace by several new header files under sched/. There have been some sneak inclusion paths via os_internal.h, so expect a few compilation errors for some architectures
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2014-08-08 18:39:28 -06:00 |
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Gregory Nutt
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99639f2d48
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SAM3/4 Interrupt initialization. Default interrupt priority not being set correctly
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2014-04-17 14:02:22 -06:00 |
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Gregory Nutt
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b8ea1d49a8
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SAM3/4: Rename CONFIG_GPIO*_IRQ to CONFIG_SAM34_GPIO*_IRQ
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2014-03-23 15:51:08 -06:00 |
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Gregory Nutt
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1061e67f14
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Fix error in last ARMv7-M up_disable_irq checkin
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2014-01-15 15:26:32 -06:00 |
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Gregory Nutt
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e43f86071d
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Fix all Cortex-M3/4 implementations of up_disable_irq(). They were doing nothing. Thanks to Manuel Stühn for the tip.
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2014-01-15 09:56:30 -06:00 |
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Gregory Nutt
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4de5e40669
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Individual IRQs are not longer disabled on each interrupt. See ChangeLog for detailed explanation
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2014-01-15 08:09:19 -06:00 |
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Gregory Nutt
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29c43b0b24
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Fixes a few more high priority, nested interrupt logic
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2013-12-23 11:13:56 -06:00 |
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Gregory Nutt
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3855ce04e8
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Beginning of high priority nested interrupt support for the ARMv7-M family
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2013-12-21 11:03:38 -06:00 |
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Gregory Nutt
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8b317e9ea3
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Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts
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2013-08-03 08:22:37 -06:00 |
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Gregory Nutt
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677365210e
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SAM4S: Add NSH configuration. Calibrated delay loops. Port now seems fully functional
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2013-06-12 10:56:42 -06:00 |
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Gregory Nutt
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617a0225cc
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SAM4L: Extend interrupt support for the larger number of NVIC interrupts of the SAM4L
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2013-06-09 13:00:38 -06:00 |
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Gregory Nutt
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e9859095dc
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Rename sam3u/ architecture directories to sam34/ to include the SAM4L
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2013-06-02 13:57:22 -06:00 |
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