Commit Graph

424 Commits

Author SHA1 Message Date
Xiang Xiao
9836c6be9b boards: Remove CONFIG_CLOCK_MONOTONIC from all defconfig
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-23 01:21:26 +08:00
Xiang Xiao
163fe4ff0b boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 21:15:36 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 20:10:14 +01:00
Huang Qi
0c5aff9be6 risc-v/qemu-rv: Supports SMP up to 8 cores
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-18 13:25:01 +08:00
Alan Rosenthal
8defb843aa Remove duplicate linker script definitions
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.

This PR cleans up the logic so they're only listed once.

 ## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!

 ## Testing
CI will test all build
2022-02-17 02:55:25 +08:00
Huang Qi
f40a673fdf boards/rv-virt: Supports FPU test and ostest in both rv32/rv64
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-17 01:09:51 +08:00
Xiang Xiao
b0fa232918 boards: Remove -D__NuttX__ from the individual Make.defs
since it is defined globally in tools/Config.mk now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-15 15:26:38 +01:00
Masayuki Ishikawa
613cbbf688 boards: risc-v: Move -fno-common option to ARCHCFLAGS/ARCHCXXFLAGS
Summary:
- Apply the same style as sabre-6quad

Impact:
- None
- NOTE: esp32c3-devkit still remains old style because of link errors

Testing:
- Build only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-15 16:27:53 +08:00
Huang Qi
ae3fa5cfbf boards/k210: Add -mstrict-align to arch level flags since it don't support unaligned memory access
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-14 11:32:34 +08:00
Huang Qi
64130b4775 risc-v: Use _ebss instead of _default_stack_limit as idle stack base
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-13 14:37:57 +08:00
Huang Qi
ef3219e83d boards: Refresh all configs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit"
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-02-09 21:21:43 +08:00
Xiang Xiao
0499979908 sched: Disable pthread by default when DEFAULT_SMALL is enabled
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-07 12:04:03 +08:00
Xiang Xiao
a9d7a776c4 sched: Remove SDCLONE_DISABLE option and config
since the related code was removed by:
commit 4d5a964f29
Author: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
Date:   Tue Feb 23 18:04:13 2021 +0800

    net: unify socket into file descriptor

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-31 19:03:20 +01:00
Ville Juven
7c116efe05 Add support for a ROMFS image for MPFS
The image must be placed into:
boards/risc-v/mpfs/icicle/include/boot_romfsimg.h

The image is mounted by mpfs_bringup, which is run by the application
itself, or by board_late_initialize() in the case when
CONFIG_BOARD_LATE_INITIALIZE is defined, e.g. with CONFIG_BUILD_KERNEL
2022-01-27 11:06:43 -03:00
Huang Qi
0c28fe9831 boards: Remove unused NXFLAT flags from Make.defs
Since NXFLAT only avaliable on arm.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-27 11:08:43 +08:00
Ville Juven
8a4881c4e5 Implement CONFIG_BUILD_PROTECTED with MMU
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW

This frees the PMP for other use, e.g. HART memory separation.

The page tables are statically allocated, 1 per level.

This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).

If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.

A more flexible solution for PMP configuration will follow.
2022-01-25 20:22:34 +08:00
Ville Juven
7eb726d57f Add proper user/kernel space linker scripts for knsh target
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.

Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
2022-01-25 20:22:34 +08:00
Ville Juven
356ae984ac Add knsh target for icicle
Template for knsh target (e.g. protected build with user space nsh)

Requires MPU and linker script updates to work
2022-01-25 20:22:34 +08:00
Ville Juven
3fa0834e7d Fix PROTECTED_BUILD build errors for mpfs target
Userspace struct definition did not have pthread_startup
The definition for up_pthread_exit was not compiled ever
2022-01-25 20:22:34 +08:00
Eero Nurkkala
e5a9ba5602 risc-v/mpfs: opensbi defconfig: refresh config
Some of the configuration options have changed, so update this
config file accordingly.

In this example config, the following hart configuration takes
place:
  hart1: 0xafb00000 (Another NuttX)
  hart2: unused
  hart3: 0x80200000 (u-boot and Linux kernel)
  hart4: 0x80200000 (u-boot and Linux kernel)

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-24 23:25:53 +08:00
Xiang Xiao
04297c3ca3 board: Remove -fno-omit-frame-pointer from Make.defs
except sim arch, since this flag is set inside Toolschain.defs now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Xiang Xiao
c5c50acb93 board: Remove -fstrict-volatile-bitfields
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Xiang Xiao
3e28192b2f board/bl602: Remove -fshort-enums
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Jukka Laitinen
fc3167b584 boards/riscv/mpfs: Remove reference to .vectors in linker scripts
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.

Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-20 01:37:34 +08:00
Xiang Xiao
8bcdefafc9 board: Remove -fno-strength-reduce
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-19 00:14:03 +01:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-16 11:11:14 -03:00
Huang Qi
5792d851e5 arch/risc-v/qemu-rv: Support both rv32/rv64 core
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-15 11:42:01 +08:00
Eero Nurkkala
c67a1a4de1 risc-v/mpfs: ld-envm-opensbi.script: add all opensbi code to .text.sbi
Add the rest of the OpenSBI code to .text.sbi -section. They belong
to there. This frees up some space in the very limited eNVM.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-14 10:10:24 +01:00
Eero Nurkkala
76c6ccc732 risc-v/mpfs: opensbi/defconfig fix RAM start address
RAM is expected to start from 0x08000000, not from
0x80000000 in this case. DDR starts from 0x80000000.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-14 10:10:24 +01:00
Huang Qi
10bb48b9b4 arch/risc-v: Merge rv32im and rv64gc into common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-11 23:24:33 +08:00
Eero Nurkkala
b4d2944df7 tools/mpfs: prepare OpenSBI image
Polarfire Icicle board has only (128K - 256) bytes for the bootloader
in the non-volatile eNVM. This space is barely enough for running NuttX.
If OpenSBI is selected, it will be placed in DDR. This all means the
nuttx.bin file grows into gigabyte size, filling the unused space (ddr -
envm) with zeroes.

The memory layout is as follows:

MEMORY
{
    ddr  (rx)          : ORIGIN = 0x80000000, LENGTH = 4M
    envm (rx)          : ORIGIN = 0x20220100, LENGTH = 128K - 256
    l2lim  (rwx)       : ORIGIN = 0x08000000, LENGTH = 1024k
    l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k
}

OpenSBI library is used as a separate binary, which is stored into
eMMC or SD-card. It is then loaded into its precise location in DDR.

Thus, we separate OpenSBI from NuttX and end up with two images
by utilizing the objcopy options:

  --only-section=sectionpattern (-j in short)
  --remove-section=sectionpattern (-R in short)

This is only valid when CONFIG_MPFS_OPENSBI is set.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-04 19:45:14 +08:00
Gustavo Henrique Nihei
cff2bc05e0 esp32c3-devkit: Restrict FS options when Flash Encryption is enabled
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
25f2dc2077 risc-v/esp32c3: Enable the creation of encrypted Flash partitions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-01 20:37:44 +08:00
Masayuki Ishikawa
98899ffe11 boards: hifive1-revb: Enable some nsh commands in nsh/defconfig
Summary:
- I noticed that most of nsh commands are disabled by default
  due to the recent changes for CONFIG_MM_SMALL=y in apps.
- This commit re-enables some nsh commands.

Impact:
- None

Testing:
- Tested with QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-01-01 20:35:27 +08:00
Dong Heng
c56c58020a risc-v/esp32c3: SPI flash MTD device uses all flash space 2021-12-31 11:40:23 +08:00
Jukka Laitinen
6f413c8654 board icicle/opensbi: Reduce image size slightly
Drop somme fancy nsh features

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Jukka Laitinen
3beecbe905 risc-v/mpfs: Add MSSIO GPIO pinmap configuration
Add a pinmap header for mpfs to be able to configure MSSIO GPIOs
This also adds Kconfigs for some different chip/package types of the PolarFire SOC

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-30 11:49:00 +08:00
Petro Karashchenko
438a62c4fc boards/arm/samv7: improve progmem common interface
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-30 10:29:36 +08:00
Jukka Laitinen
fc41bb7f8a boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET
This fixes problems with DDR training sequence on aries m100pfs board

    - Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2)
    - Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-12-29 09:36:49 -06:00
Huang Qi
d71cfc178a arch/risc-v: Remove unneeded kconfigs
CONFIG_RV32IM_HW_MULDIV can be safely removed since this behavior is
controlled by M extension.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 05:02:42 -06:00
Huang Qi
c2e8c92b25 arch/risc-v: Refine Toolchain.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-28 00:30:10 -06:00
chao.an
cbd82f1c1b compile/flags: remove redundant -fomit-frame-pointer from board flags
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-12-27 22:31:27 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-27 21:01:19 -06:00
ligd
412d030149 boards: move USERMAIN_XX out of INIT_ENTRYPOINT
Signed-off-by: ligd <liguiding1@xiaomi.com>
2021-12-24 08:23:30 -06:00
Eero Nurkkala
509350a614 risc-v/mpfs: update m100pfsevp board info
Update the cache settings for the Aries m100pfsevp board. This
assigns scratchpad ways for this board as well, as seen in the
commit 491ae6c.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-23 06:55:18 -06:00
Eero Nurkkala
b128ce334f mpfs: introduce OpenSBI
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.

OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.

OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.

Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:

  opensbi_reserved: opensbi@80000000 {
      reg = <0x80000000 0x200000>;
      label = "opensbi-reserved";
  };

The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
Eero Nurkkala
491ae6cc53 mpfs: cache: assign ways to L2 zero device
Assign ways to L2 zerodevice. L2 zero device is used for
the scratchpad functionality. The area may be used for the
harts communicating to each other.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-12-22 20:48:12 -06:00
zhanghu6
d05b9a9c79 note dump: add CONFIG_SCHED_INSTRUMENTATION_SWITCH
1. If CONFIG_SCHED_INSTRUMENTATION_SWITCH is enabled, then these additional interfaces are expected:
        sched_note_suspend
        sched_note_resume
at the same time,If CONFIG_SMP is enabled,then expected:
        sched_note_cpu_pause
        sched_note_cpu_paused
        sched_note_cpu_resume
        sched_note_cpu_resumed
2. other board if enable SCHED_INSTRUMENTATION,SCHED_INSTRUMENTATION_SWITCH to defconfig.
2021-12-15 07:07:00 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2021-12-14 07:32:48 -06:00
Huang Qi
8ce3337e85 arch/risc-v: Implement TLS support
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-12 10:19:00 -06:00
Jari van Ewijk
2e47ef32cf GPIO driver: register all pintypes as generic /dev/gpioN 2021-12-09 23:55:12 -06:00
Huang Qi
3d4be7089c drivers/serial/uart_16550: Fix warning for format
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-07 23:28:33 -06:00
Huang Qi
63ab2f4308 arch/risc-v: Introduce basic support for qemu rv32
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-12-07 23:28:33 -06:00
Dong Heng
698f1f76ff risc-v/esp32c3: Refactor SPI Flash to support umask interrupt when R/W/E SPI Flash
This can fix BLE assert when erase SPI Flash.
2021-12-06 13:13:11 +09:00
Jukka Laitinen
ac5a228d89 boards/risc-v/mpfs: Enable CONFIG_SPI_CS_CONTROL
Enable CS control via register write for the mpfs hwtest target

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2021-11-24 06:50:32 -06:00
Xiang Xiao
ea0aadff1e boards/mpfs: Fix the icicle build break
src/mpfs_emmcsd.c: In function 'mpfs_board_emmcsd_init':
Error: src/mpfs_emmcsd.c:72:40: error: 'SDIO_SLOTNO' undeclared (first use in this function)
   finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO);
                                        ^~~~~~~~~~~
src/mpfs_emmcsd.c:72:40: note: each undeclared identifier is reported only once for each function it appears in
Error: src/mpfs_emmcsd.c:83:55: error: 'SDIO_MINOR' undeclared (first use in this function); did you mean 'SHRT_MIN'?
   finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR);

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-18 11:45:50 -06:00
Jani Paalijarvi
6dd4d5de15 risc-v/mpfs: Add support for Aries M100PFSMVP board
- Add defconfig and board specific files
- Create mpfs/common for code which is shared between MPFS boards.
- Add support for GPIO driven EMMCSD mux.
- Move DDR Libero definitions from arch to boards.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2021-11-18 10:59:44 -03:00
Dong Heng
779a29fea5 boards/Kconfig: set BOARD_ASSERT_RESET_VALUE default value to be 1
The board code should separate the reset reason, so it had better
make "BOARD_ASSERT_RESET_VALUE" not be equal to "EXIT_SUCCESS".
2021-11-16 10:44:54 -03:00
Dong Heng
92eedd93a7 risc-v/esp32c3: Fix reset triggering crash nested when crash 2021-11-16 10:44:54 -03:00
Abdelatif Guettouche
a01cb867ce esp32c3_rom.ld: Add some of the string.h functions to the linker
script.

These functions are strongly declared and thus will be used instead of
any other implementation.  Furthermore, necessary Kconfig options are
selected to avoid building those function from NuttX's C library.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-13 11:54:42 -03:00
Xiang Xiao
0aeb132d15 board: Run ./tools/refresh.sh --silent all
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-10 09:16:35 +01:00
Abdelatif Guettouche
044508c979 boards/esp32c3-devkit: Add a defconfig for the USB CDC Console.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-09 09:22:57 -03:00
Xiang Xiao
3847539f3d board: Run ./tools/refresh.sh --silent all
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-11-07 13:19:15 +01:00
ChenWen
440787c0c1 risc-v/esp32c3: Fix Wi-Fi & BLE coexist issue
1. Wi-Fi and BLE use common PHY functions.
  2. Fix Wi-Fi & BLE coexist adapter error.
  3. Update esp-wireless-drivers-3rdparty, provide coexist protection for connection.
2021-11-04 11:02:05 -03:00
Eero Nurkkala
8e43f39141 mpfs: cache: provide L1/L2 cache enablers
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.

L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.

mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-04 11:00:55 -03:00
Jani Paalijarvi
a16a9f80e2 mpfs: i2c: Add support for adaptive I2C bus frequency
Select the closest possible frequency which is smaller
than or equal to requested in I2C msg
2021-11-02 04:10:08 -05:00
Abdelatif Guettouche
860370284e esp32c3_dma: Remove the DMA test included in the driver along with its
defconfig.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-11-01 13:49:59 -05:00
Gustavo Henrique Nihei
c9d784a238 boards/esp32c3-devkit: Port SPI Flash FS fixes from ESP32
This commit brings 3 fixes/improvements applied to the Kconfig options
for SPI Flash file system support on board bring-up:
- (925e8f9) Optionally mount SPI Flash MTD on bring-up
- (f74c6f7) Transform SPI Flash FS deps into reverse deps
- (9056cab) Select MTD_SMART if SmartFS is selected for SPI Flash MTD

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
18f785c7b7 risc-v/esp32c3: Removed unused definitions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
06bb85d8a5 risc-v/esp32c3: Rename MTD-related configs to become more intuitive
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 21:45:20 -05:00
Gustavo Henrique Nihei
211f899b62 risc-v/esp32c3: Refactor and reorganize Partition Table related configs
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-25 16:34:58 -03:00
Eero Nurkkala
c7cf9fd9d2 mpfs: board Make.defs: add bootloader linker option
Use the linker script used with bootloaders that start
from the eNVM.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-10-21 22:40:26 -05:00
Eero Nurkkala
ad76b6733c mpfs: boards: add ld-envm.script
This configuration is used when flashing nuttx as a bootloader
in the eNVM region.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-10-21 22:40:26 -05:00
Eero Nurkkala
3b330089d5 mpfs: ddr: add DDR training
This adds DDR training. The training has a small chance of failing,
and then the training is restarted.

DDR training cannot be done meaningfully while the software is
in DDR. If the system is intended to run from eNVM, like a
bootloader, the linker script should be tuned to utilize the envm
region as follows:

  envm (rx)   : ORIGIN = 0x20220100, LENGTH = 128K - 256
  l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 1024k

256 bytes are reserved for the system; The fixed block may be
installed from the 'hart-software-services' -repository:
https://github.com/polarfire-soc/hart-software-services.git

For example, the 256-byte image: hss-envm-wrapper-bm1-dummySbic.bin
may be prepended on the nuttx bootloader image in the following
manner:

 cat hss-envm-wrapper-bm1-dummySbic.bin > nuttx_bootloader.bin
 cat nuttx.bin >> nuttx_bootloader.bin
 riscv64-unknown-elf-objcopy -I binary -O ihex --change-section-lma
  *+0x20220000 nuttx_bootloader.bin flashable_image.hex

This provides an image 'flashable_image.hex' that may be flashed on
the eNVM region via Microsemi Libero tool.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-10-21 22:40:26 -05:00
Abdelatif Guettouche
9235d6605b boards/esp32&esp32c3: Remove crypto accelerators' defconfigs.
Since the tests were removed from the drivers, there is no need for
these defconfigs anymore.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
55e8b17974 boards/risc-v/esp32c3: Remove the flash encryption test.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
e424241d09 arch/risc-v/esp32c3: Remove the bignum test from the driver.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
91cb9dafaf arch/risc-v/esp32c3: Remove the RSA test from the driver.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
652d77efd2 arch/risc-v/esp32c3: Remove the SHA test from the driver.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-19 18:41:57 -03:00
Abdelatif Guettouche
5d1c01aea7 arch/risc-v/esp32c3: Remove the AES test from the driver.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-19 18:41:57 -03:00
Matheus Castello
5c15fe6ec1 boards: k210: Add initial gpio user space support
Signed-off-by: Matheus Castello <matheus@castello.eng.br>
2021-10-17 17:29:59 +09:00
Matheus Castello
1bc3ab513d boards: risc-v: k210: Fix -march and -mabi
-march=rv64gc -mabi=lp64 does not resolve lib paths for
riscv64-unknown-elf-gcc resulting in lib not found errors.
Changing it to -march=rv64imafc -mabi=lp64f that is the default
used in Sipeed repositories.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
2021-10-14 15:50:20 +09:00
jsun
c58fddb915 Open ble controller adaptation code
N/A

Signed-off-by: jsun <jsun@bouffalolab.com>
2021-10-08 02:30:27 -07:00
Gustavo Henrique Nihei
0a1b3c1331 risc-v/esp32c3-devkit: Add BLE defconfig
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-05 08:45:40 -03:00
Gustavo Henrique Nihei
47e804b167 risc-v/esp32c3: Make BLE adapter code compliant to nxstyle
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-10-05 08:45:40 -03:00
Abdelatif Guettouche
ee20d0f545 esp32c3_rom.ld: Add a strong declaration to some libgcc function that
are ROM resident.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-10-01 10:09:04 -03:00
Gustavo Henrique Nihei
548f2b6eab boards/esp32c3-devkit: Add mcuboot_confirm defconfig
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-27 18:22:29 -07:00
Gustavo Henrique Nihei
3c63cb522c risc-v/esp32c3: Enable booting from MCUboot bootloader
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-27 18:22:29 -07:00
Alan C. Assis
f9b322567c boards/esp32c3: Remove "return ret" from bringup 2021-09-21 10:34:55 -03:00
Alan C. Assis
63a17f5cdd esp32c3-devkit: Add board profile to use LVGL on GC9A01 display 2021-09-18 20:58:30 -05:00
Janne Rosberg
e022ea1283 mpfs/icicle/configs/hwtest: enable SD card 2021-09-18 12:18:09 -03:00
Eero Nurkkala
812f504c16 mpfs: emmcsd: add Kconfig/Makefile and board files
Add necessary Kconfig, Make.defs, Makefile and board
file changes.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-09-18 12:18:09 -03:00
Peter Bee
a7a3d8bec7 boards/esp32c3: add ESP32C3 LCD drivers
Add board driver for ST7735, ST7789 and GC9A01

Signed-off-by: Peter Bee <bijunda1@xiaomi.com>
2021-09-17 09:35:10 -03:00
Alan C. Assis
099e9fb4f7 boards: Remove -nostartfiles -nodefaultlibs from LDFLAGS 2021-09-13 08:58:25 +08:00
Janne Rosberg
d361a9ded8 boards/icicle: add hwtest config
This config enables all peripherals and some tools.
Also useful for CI build check.
2021-09-11 23:33:01 +08:00
Sara Souza
acf18bd82d risc-v/esp32-c3: refactor the Wi-Fi board logic.
This commit moves the Wi-Fi initialization to
Wi-Fi specific file and to spiflash initialization.

It also reserves one partition for Wi-Fi use and for general use,
and makes it possible to me mounted by several FS.
2021-09-09 20:14:04 +08:00
Sara Souza
11068fad1b risc-v/esp32-c3: Enable the allocation of multiple MTD SPI Flash partitions 2021-09-09 20:14:04 +08:00
Gustavo Henrique Nihei
310a2dd0e4 tools/esp32c3: Create option for merging all binaries into a single file
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2021-09-08 12:16:52 +02:00
Alin Jerpelea
9d870e1502 defconfig: allow use of BSD components
several configs are used for testing and need the BSD components

more information about license can be found here
https://www.apache.org/legal/resolved.html#category-a

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-09-02 09:00:43 -03:00
Alin Jerpelea
2ab9e7fef0 Revert "esp32: remove FS_SPIFFS from defconfigs"
This reverts commit 35a004bdd0.
2021-09-02 09:00:43 -03:00
Alin Jerpelea
35a004bdd0 esp32: remove FS_SPIFFS from defconfigs
FS_SPIFFS uses BSD license and should not be enabled by default

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-30 22:39:04 +08:00
Xiang Xiao
e3ab1179fa board: Enable CONFIG_LIBCXXABI when CONFIG_LIBCXX is enabled
to avoid link libsupc++.a which is provided by toolchain

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-28 17:13:43 -03:00
Alin Jerpelea
a43650648e risc-V: remove ble defconfigs
By default the components with BSD license should be disabled

NOTE:
the BLUETOOTH components was enabled in a non bluetooth config

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-08-27 02:56:22 +08:00
Antti Vähälummukka
6eb73ced51 arch/risc-v/src/mpfs: Add CorePWM driver
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA

This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
2021-08-20 08:56:30 -03:00
Xiang Xiao
b12f588140 Rename CONFIG_LIB_BOARDCTL to CONFIG_BOARDCTL
since boardctl isn't a libc feature

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-06 13:58:26 +02:00
Xiang Xiao
5025fbef8d Rename LIB_ to LIBC_ for all libc Kconfig
follow other libc component naming convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-08-05 19:45:24 +02:00
Xiang Xiao
007adc7736 Replace all __attribute__((section(x)) with locate_data(x)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-29 21:55:21 -03:00
jordi
b87333bae8 Kconfig: remove empty help sections
To avoid the setconfig warning: "has 'help' but empty help text"
2021-07-23 02:32:19 -07:00
Alan C. Assis
b9ec0063bc Remove duplicated Documentation of the bl602evb 2021-07-19 06:26:52 -07:00
Sara Souza
81e881c8c0 risc-v/esp32-c3: Makes output readable and rmv unnecessary var. 2021-07-16 19:53:04 -03:00
Virus.V
063e1d6b74 risc-v/bl602: update wifi firmware and some fixup.
1. Added check for repeated connection wifi operations.
2. Invoke the carrier on/off operation in the wrong place.
3. The RTC initialization time is incorrect.
4. Reserve 32K I-Cache space in the linker script.
5. Increase the size of the wifi firmware receiving buffer.

Signed-off-by: Virus.V <virusv@live.com>
2021-07-13 05:12:12 -07:00
Virus.V
4e950c3e30 risc-v/bl602: add boardctl support
Signed-off-by: Virus.V <virusv@live.com>
Change-Id: I74280f5cb801e923fb987009ae007aa02677b14d
2021-07-13 02:50:40 -07:00
Dong Heng
f5eaf82c93 risc-v/esp32c3: Use onexit to free thread private semaphore 2021-07-12 09:38:21 -03:00
Jiuzhu Dong
85470176e7 sched/task: delete CONFIG_MAX_TASKS limit
Change-Id: I583015a95dbcebd352f81ecb3104ffdbd646a9ec
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2021-07-11 19:42:30 -07:00
Dong Heng
d83caef2df boards/esp32c3-devkit: Support mounting SPI Flash MTD to littleFS 2021-07-08 09:01:43 -03:00
Dong Heng
2d6c1044fb boards/esp32c3-devkit: Fix compiling error
Add UID defconfig to check compiling error.
2021-07-07 02:49:52 -05:00
Xiang Xiao
f0961f43a6 boards/esp32c3-devkit: Add etctmp to .gitignore
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-06 09:49:43 -05:00
chenwen
97b8e90d79 boards/esp32c3: Add romfs configuration 2021-07-06 05:25:14 -05:00
Dong Heng
475becac37 risc-v/esp32c3: Add board_ioctl and board_uniqueid 2021-07-05 23:12:17 -05:00
Nathan Hartman
ce20211357 Fix various typos in comments and documentation
Fix typos in these files:
    * Documentation/components/drivers/character/foc.rst
    * Documentation/guides/cpp_cmake.rst
    * Kconfig
    * arch/arm/src/imxrt/imxrt_lpspi.c
    * arch/arm/src/kinetis/kinetis_spi.c
    * arch/arm/src/kl/kl_spi.c
    * arch/arm/src/lpc31xx/lpc31_spi.c
    * arch/arm/src/nrf52/nrf52_radio.h
    * arch/arm/src/s32k1xx/s32k1xx_lpspi.c
    * arch/arm/src/stm32/Kconfig
    * arch/arm/src/stm32/stm32_adc.c
    * arch/arm/src/stm32/stm32_foc.c
    * arch/arm/src/stm32/stm32_foc.h
    * arch/arm/src/stm32/stm32_pwm.c
    * arch/arm/src/stm32/stm32_spi.c
    * arch/arm/src/stm32f0l0g0/stm32_spi.c
    * arch/arm/src/stm32f7/Kconfig
    * arch/arm/src/stm32f7/stm32_spi.c
    * arch/arm/src/stm32h7/Kconfig
    * arch/arm/src/stm32h7/stm32_allocateheap.c
    * arch/arm/src/stm32h7/stm32_fmc.c
    * arch/arm/src/stm32h7/stm32_fmc.h
    * arch/arm/src/stm32h7/stm32_pwm.c
    * arch/arm/src/stm32h7/stm32_qspi.c
    * arch/arm/src/stm32h7/stm32_spi.c
    * arch/arm/src/stm32l4/stm32l4_pwm.c
    * arch/arm/src/stm32l4/stm32l4_spi.c
    * arch/arm/src/stm32l5/Kconfig
    * arch/arm/src/stm32l5/stm32l5_spi.c
    * arch/renesas/src/rx65n/rx65n_dtc.c
    * arch/renesas/src/rx65n/rx65n_usbdev.c
    * arch/risc-v/src/rv32m1/rv32m1_serial.c
    * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c
    * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c
    * boards/arm/stm32h7/nucleo-h743zi2/README.txt
    * boards/risc-v/rv32m1/rv32m1-vega/README.txt
    * boards/sim/sim/sim/scripts/Make.defs
    * drivers/1wire/1wire.c
    * drivers/1wire/1wire_internal.h
    * drivers/lcd/Kconfig
    * drivers/syslog/ramlog.c
    * fs/fat/Kconfig
    * libs/libc/debug/Kconfig
    * libs/libc/machine/Kconfig
    * libs/libc/stdio/lib_libvsprintf.c
    * libs/libc/stdlib/lib_div.c
    * libs/libc/stdlib/lib_ldiv.c
    * libs/libc/stdlib/lib_lldiv.c
    * libs/libdsp/lib_observer.c
2021-07-04 11:23:26 -05:00
Xiang Xiao
1b5341f6c0 boards/bl602: Fix uart_nx.c:419: undefined reference to `uart_bth4_register'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-07-01 05:01:21 -05:00
xiewenxiang
5fd3eca9c9 riscv/esp32c3: Support BLE sleep mode 2021-06-28 23:14:30 -05:00
xiewenxiang
145d917587 riscv/esp32c3: Add Wi-Fi and BLE coexist 2021-06-28 23:14:30 -05:00
xiewenxiang
8b96edc3a5 riscv/esp32c3: Add esp32c3 BLE driver 2021-06-28 23:14:30 -05:00
Virus.V
8452c571ec risc-v/bl602: BLE firmware adapts to the new framework
Signed-off-by: Virus.V <virusv@live.com>
2021-06-28 07:03:04 -05:00
Virus.V
cd50650583 risc-v/bl602: Support AP and STA as independent network interface device
Signed-off-by: Virus.V <virusv@live.com>
2021-06-28 07:03:04 -05:00
Abdelatif Guettouche
11ed8575cd boards/rsic-v/esp32c3: Use the common gnu-elf.ld file from binfmt/libelf
instead of keeping the same file for each board.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-24 08:04:14 -05:00
Abdelatif Guettouche
eb403bc996 boards/riscv/esp32c3: Rename the iram_0_2 segment to irom_0_0 to avoid
confusions.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-24 07:00:51 -05:00
Abdelatif Guettouche
60da4317b9 arch/risc-v/esp32c3: Use the same naming for the RTC heap as ESP32 for
consistency.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-23 08:37:01 +09:00
Liu Han
2dd081ed7d risc-v/esp32c3: Support ESP32-C3 SHA accelerator 2021-06-21 02:41:53 -05:00
Abdelatif Guettouche
af5e0c620f Rename MODULE_TEXT to TEXT_HEAP as the latter is more generic.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 07:14:17 -05:00
Abdelatif Guettouche
f54804bafc arch/risc-v/esp32c3: Create a separate heap for the RTC memory.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
965a39a76d boards/risc-v/esp32c3-devkit: Include "config.h" in esp32c3_boot.c
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
bd0e03fecf boards/risc-v/esp32c3-devkit/esp32c3.ld: Add the RTC BSS section for
completeness.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 00:53:42 -05:00
Abdelatif Guettouche
61f7bc6e2a boards/risc-v/esp32c3-devkit/scripts: Drop the "iram" in the name of the RTC
section.

The RTC region is accessed by both I and D buses.  The old name of
`rtc_iram_seg` is a bit confusing.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-18 00:53:42 -05:00
Liu Han
04c805207a risc-v/esp32c3: Support ESP32-C3 efuse 2021-06-16 09:35:09 -03:00
Liu Han
8eaaf6d462 risc-v/esp32c3: Support ESP32-C3 RSA accelerator 2021-06-14 15:03:11 -03:00
Eero Nurkkala
1bce864ef7 mpfs: add i2c driver
This adds mpfs i2c driver.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-06-11 21:03:42 -05:00
Eero Nurkkala
fad34e04c4 mpfs: add spi driver
This adds the SPI driver for the MPFS Icicle board.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-06-11 09:10:03 -05:00
Chen Wen
dbf9c87a42 risc-v/esp32c3: Support ESP32-C3 RTC driver 2021-06-10 09:33:04 -03:00
Xiang Xiao
5b2a17b892 Include assert.h in necessary place
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-08 13:06:08 -07:00
unixjet
68f19a6290 risc-v/rv32m1: Basic port to rv32m1 ri5cy 2021-06-05 17:25:57 -03:00
Gustavo Henrique Nihei
0b3c2c7603 spi: Refactor SPI Slave interface prefix to sync with I2C Slave 2021-06-05 04:50:34 -07:00
Abdelatif Guettouche
f00deae9ac boards/esp32c3-devkit: Add a defconfig to test the shared library
example.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-04 18:08:36 -03:00
Abdelatif Guettouche
dd4962b2f8 boards/esp32c3-devkit: Add the necessary flags for loadable modules and
a module defconfig to test the "module" example.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-04 18:08:36 -03:00
Abdelatif Guettouche
3b7ae20843 boards/risc-v/esp32c3-devkit: Add an ELF defconfig and the necessary ELF
flags and linker script to support that.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2021-06-04 18:08:36 -03:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-03 08:36:03 -07:00
YAMAMOTO Takashi
c20ed229b1 refresh configs 2021-06-03 10:05:33 -05:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-06-01 06:42:02 +09:00