Ilya Averyanov
f2b5f05124
STM32 Ethernet: stm32_ifdown() prototyped twice
2015-09-02 08:23:45 -06:00
Gregory Nutt
5a9f1fa3ab
Extension memory map inclusion for SAMA5D2
2015-09-02 08:23:44 -06:00
Gregory Nutt
075b66d4bb
Eliminate a warning
2015-09-01 13:35:38 -06:00
Gregory Nutt
8c9f7e5ab6
Add peripheral clock macros for the SAMA5D2
2015-09-01 13:08:48 -06:00
Gregory Nutt
f6d8a03b55
Merged in paulpatience/nuttx-arch (pull request #10 )
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Correct #if to #ifdef when the macro can be undefined. Fix bug in AT32UC3 clock initialization: AVR32_CLOCK_PLL_OSC1 should be AVR32_CLOCK_PLL0_OSC1 and AVR32_CLOCK_PLL1_OSC1.
2015-09-01 12:31:05 -06:00
Paul A. Patience
a0dc724a5d
Correct #if to #ifdef when the macro can be undefined. Fix bug in AT32UC3 clock initialization: AVR32_CLOCK_PLL_OSC1 should be AVR32_CLOCK_PLL0_OSC1 and AVR32_CLOCK_PLL1_OSC1.
2015-09-01 13:47:06 -04:00
Ilya Averyanov
98788063f1
Fix warning in Kconfig file introduced with first SAMA5D2 commit. From Ilya Averyanov.
2015-09-01 11:23:08 -06:00
Gregory Nutt
ed3d6fc7a0
SAMV7 QSPI: Delays need to be in units of nsec, not usec. Default delays should be 0 nsec
2015-09-01 11:16:09 -06:00
Ilya Averyanov
8c52786395
LPC43xx: Fix missing #define in eeprom. From Ilya Averyanov
2015-09-01 08:08:09 -06:00
Ilya Averyanov
675878b360
PC43xx: Fix NVIC_SYSH_PRIORITY_STEP define
2015-09-01 08:06:34 -06:00
Gregory Nutt
c33efa0a60
SAMA5D2: Add chip definitions, PIDs, and IRQ definitions
2015-08-31 15:19:01 -06:00
Gregory Nutt
9ba349f2b8
SAMV71 QSPI: Fix frequency calculation. Need to use ceil() type logic so that requested frequency is not exceeded
2015-08-31 10:18:17 -06:00
Gregory Nutt
4f87a71e6d
SAMV7 QSPI: Use of CPHA in mode settings was inverted
2015-08-31 10:05:41 -06:00
Gregory Nutt
4b738ba7cc
SAMV7 QSPI: Fix some compiler problems when SPI debug is enabled
2015-08-31 08:57:30 -06:00
Gregory Nutt
70f1a49fbe
arch/arm/src/up_iternal.h and several ARM Make.defs files: In the original implementation, NOT defined(CONFIG_ARMV7M_CMNVECTOR) was a sufficient test to determine if lazy floating point register saving was being used. But recents changes added common lazy register as well so now that test must be (NOT defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU)).
2015-08-31 08:40:02 -06:00
Gregory Nutt
b6515bbd4d
SAMV71 QSPI: Changes resulting removing of clocking
2015-08-29 18:53:27 -06:00
Gregory Nutt
b94eef2f19
SAMV71 QSPI: Driver is code complete
2015-08-29 15:57:20 -06:00
Gregory Nutt
3877cb09d9
Trivial renaming
2015-08-29 10:04:36 -06:00
Gregory Nutt
b887d39d2e
SAMV7 QSPI: Add DMA transfer support
2015-08-29 10:02:59 -06:00
Gregory Nutt
0b1bd46e24
SAMV71 QSPI: Add support for dual and quad data transfers and dummy read cycles
2015-08-28 11:58:19 -06:00
Gregory Nutt
3e0affba86
SAMV71 QSPI: Add support for non-DMA memory transfers
2015-08-28 10:13:46 -06:00
Gregory Nutt
8aefb9d139
SAMV71 QSPI: Redesign some functions to better matched new interface definition
2015-08-27 14:15:23 -06:00
Gregory Nutt
71bbe5b48d
Merge remote-tracking branch 'origin/master' into st25fl1
2015-08-27 12:08:04 -06:00
Gregory Nutt
926f3aa9af
Update some comments
2015-08-27 08:19:26 -06:00
Gregory Nutt
45a6f79eeb
SAMV71 QSPI: Flesh out most of the initialization logic
2015-08-26 14:15:40 -06:00
Gregory Nutt
768aba20ad
SAMV71 QSPI: Use new QSPI interface. Can't use SPI interface as planned; the hardware architectue is too different
2015-08-25 15:23:59 -06:00
Gregory Nutt
fa9522da41
Missed one file in last commit
2015-08-24 14:30:58 -06:00
Gregory Nutt
01cfe8c315
Networking: Move where the local loopback device is initialized from board_app_intiialize() to up_intiialize() so that it will happen automatically
2015-08-24 14:25:49 -06:00
Gregory Nutt
0732914d09
Merged in david_s5/arch/upstream_446_clock (pull request #9 )
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Upstream_446_clock
2015-08-24 14:13:51 -06:00
Gregory Nutt
706d50d97a
Merge branch 'master' of bitbucket.org:nuttx/arch
2015-08-24 13:46:19 -06:00
Gregory Nutt
c9603b27c0
sim: Add logic to initialize the local loopback device is so configured
2015-08-24 13:46:05 -06:00
David Sidrane
98ce2b2912
Fixed Mask and made configuration macros consistant
2015-08-24 08:56:24 -10:00
David Sidrane
b95c642a88
Added Kconfig Enable Support for SAI and I2S PLL
2015-08-24 08:55:45 -10:00
Gregory Nutt
bddc4dbd6a
LPC17: Fix RAM vector table alignment for the LPC17 family. The ARMv7-M TRM only requires 128-byte alignment for vector tables; the LPC17, however, requires 256 byte alignment
2015-08-23 17:17:14 -06:00
Gregory Nutt
065f2d6057
SAMV7 USBHS DCD: Add logic to detect high speed mode; use DEBUGASSERT to check input parameters
2015-08-22 08:58:38 -06:00
David Sidrane
6559c8994a
Remove the word NOT - that was used to test the fix.
2015-08-21 18:51:28 -06:00
David Sidrane
390c777a2a
Removed the word NOT - that was used to test the fix.
2015-08-21 18:40:20 -06:00
Pavel Pisa
2fafe1c817
arch/arm/src/lpc17: Actually implement options to use external SDRAM and or SRAM for the heap. From Pavel Pisa
2015-08-21 18:28:59 -06:00
Gregory Nutt
4c0d36740d
Some of the last review chnages were still in the editor
2015-08-21 18:25:10 -06:00
Gregory Nutt
9a32e907df
Trivial, cosmetic changes from review of merge
2015-08-21 18:22:57 -06:00
Gregory Nutt
4e347080e6
Update comments in Kconfig file
2015-08-21 18:15:09 -06:00
Gregory Nutt
16c5be9767
Merged in david_s5/arch/upstream_446 (pull request #7 )
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Upstream_446
2015-08-21 18:11:05 -06:00
David Sidrane
9d64050d68
Added Changes to support for the new USB OTG controller for F446 register map
2015-08-21 13:57:08 -10:00
David Sidrane
7c96342c63
Break the stm32_otg.h into an stm32fxxxxx and stm32f44xx (should work on F7) versions
2015-08-21 13:55:06 -10:00
David Sidrane
5d1ff3f7e1
Use read modify write on PLL and CFG registers
2015-08-21 13:22:09 -10:00
David Sidrane
1c746edceb
Added PLL P constants
2015-08-21 13:20:16 -10:00
Gregory Nutt
972f67ce42
SAMV7 QSPI: Add framework for a QSPI driver. Initial commit is just the SPI driver with some name changes
2015-08-21 14:22:47 -06:00
Gregory Nutt
f6c6723d88
SAMV7 USBHS Device: After aligning DMA buffers and disabling write-back data cache, the DCD driver is fully functional using the CDC/ACM device
2015-08-21 12:30:29 -06:00
Gregory Nutt
da6c5aabdf
All ARMV7-M IRQ setup: Always set the NVIC vector table address. This is needed in cases where the code is running with a bootload and when the code is running from RAM. It is also needed by the logic of up_ramvec_initialize() which gets the vector base address from the NVIC. Suggested by Pavel Pisa
2015-08-21 08:42:24 -06:00
Gregory Nutt
0b3b104b74
Remove unnecessary step in previous commit
2015-08-20 16:21:45 -06:00
