Commit Graph

9 Commits

Author SHA1 Message Date
Alin Jerpelea
c39339a7a8 arch: arm: include: nxstyle fixes
nxstyle fixes to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-22 19:28:38 -07:00
Alin Jerpelea
4daa276903 arch: arm: include: Author Gregory Nutt: update licenses to Apache
Gregory Nutt has submitted the SGA and we can migrate the licenses
 to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-22 19:28:38 -07:00
Dave Marples
d0cda60442 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
9051ffd638 STM32GG Starter Kit: Add basic NSH configuration 2014-11-03 16:58:22 -06:00
Gregory Nutt
2bafdf3d59 Add EFM32 interrupt vector defintions 2014-10-17 10:34:39 -06:00
Gregory Nutt
895cfe0e7c Add configuration support for the EFM32 Gecko Starter Kit 2014-10-17 09:25:52 -06:00
Gregory Nutt
26b7316609 Remove support for EFM32. Not ready to be fielded 2014-01-27 08:03:39 -06:00
Gregory Nutt
07d12a800d Basic support for the EFM32 processor family from Richar Cochran 2014-01-23 07:56:10 -06:00