Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Copied spi flash files from risc-v
Removed old spiflash from make.defs
KConfig modifications for common spiflash
Added new spiflash entry to make.defs
S2 Board config update
Modifications working on S2. Need fix on ROM function
Board fixes
Deleted old spiflash files
Fixes for smartfs operation
Set new HAL version
Fixed wrong change on S3
Cache flush must be done prior to the APP cpu initalization. This,
however, must be true for the case where PSRAM is not available or
not selected. To do that, this commit flushs the cache during the
device initialization.
This commit fixes a deadlock in `esp32s3-devkit:sta_softap`
defconfig: `spin_lock_irqsave` was being used to enter a critical
section that calls `nxsem_post`. In this case, it's recommended
to use `[enter|leave]_critical_section` to avoid deadlocks when a
context switch may happen, for instance.
NuttX uses PSRAM, possibly using the APP_CPU cache MMU,
way before starting the APP_CPU in up_cpu_start().
Flushing the cache when launching the APP_CPU can cause
data corruptions on PSRAM.
Eg. mm_heap structures if the PSRAM is added to a heap.
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
Wait for CMDDONE in esp32s3_waitresponse even an error response is received.
Otherwise, the CMDDONE event of this command will disrupt later command.
Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Only in the non-critical region， nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be released
we also need keep restore_critical_section in svc call
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Due to the xtensa mpu feature, the size of the Region depends on the Base of the next Region. e.g.
Region[1] = 0x20000000
Region[0] = 0x30000000
Then Region[1] length = Region[0] - Region[1]
So this approach is not suitable to implement the behavior of cleaning
up the Region and such a configuration will result in affecting the very beginning (the higher) Region
Therefore, to address this feature, in this change we return the Region
value and implement the ability to modify the target Region's attributes
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Summary:
1.Modify the conditions for entering different include header files
2.Added pre-definition for _Atomic _Bool when it is missing
3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
arch/xtensa/src/esp32s3/hardware/esp32s3_sdmmc.h|esp32s3_soc.h,
boards/xtensa/esp32s3/common/include/esp32s3_board_sdmmc.h,
boards/xtensa/esp32s3/common/src/Make.defs|esp32s3_board_sdmmc.c,
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c: add SD/mmc driver
Support 1-bit bus width and 4-bit bus width. Support eMMC high speed SDR mode.
Support transfer data with DMA. Support SD clock frequency up to 40MHZ.
Signed-off-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Reviewed-by: Yuezhang Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Jacky Cao <Jacky.Cao@sony.com>
Tested-by: Yinzhe Wu <Yinzhe.Wu@sony.com>
Enabling CONFIG_PRIORITY_INHERITANCE config causes a build error
Based on Nuttx OS reserve memory for mutex struct.
Pass build based on
- CONFIG_PRIORITY_INHERITANCE y
- CONFIG_SEM_PREALLOCHOLDERS 0/8
1. For some reasons, the bootloader will set CPU source to BBPLL and enable it,
but there are calibration issues, so we need turn off the BBPLL and do calibration again to fix the issue.
2. Corresponding issue link: 89cc9084ab
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
Other ESP32-S3 modules (with embedded flash and PSRAM) were added.
Also, the `help` section of the Kconfig was updated to better
describe the modules' flash and PSRAM sizes.
Provide `up_copy_section` function that enables copying data using
the data bus. If the memory destination address is accessible
through the instruction bus, the data is copied using the
correspondent address accessible through the data bus.
The buffer initialization function (`i2s_buf_initialize`) calls
`i2s_buf_free`, which performs buffer initialization within a
critical section (`spin_lock_irqsave`). If this function is called
under the same critical section (same spinlock), initialization
will hang.
arch/xtensa: add support for capture driver on ESP32 and ESP32|S3|
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Review fixes
arch/xtensa: add support for fault signal on motor control
Squashed:
Initial settings for MCPWM Capture on board level
Created lower half files - compilation ok
Using capture debug features. Simple example on fops works
Successful duty and freq calculation
Documentation update
Fixed and added interupt capabilities for all 3 capture channels
Cleaned defconfig
Renamed macros, added S3 options and moved arch source to common dir
Added support for ESP32S3
Added capture example to defconfig and renamed
Basic bring up ready. New Kconfig options for motor.
Good motor registration
Working on enabling pwm generators
Working on enabling pwm generators
Added fops functions
Success on PWM 50%
stable pwm operation for bdc
Added loopback option for testing
Improved rules on fsm
Working motor direction control
Testing new ISR for fault handling
Issues on fault ISR
Removed fault implementation (not working)
Added support for esp32s3
Documentation improvements
Added default motor spin direction
Added parameter change while running
Got responsive fault indicator
Working brakes - still need to work on starting isr
Fixed single-time ISR initializiation
Working soft brake on fault
Improved KConfig for BDC and BLDC
Kconfig fixed at board level
when the thread to backtrace is exiting, get_tcb and up_backtrace in
different critical section may cause try to dump invalid pointer, have
to ensure the nxsched_get_tcb and up_backtrace inside same critical
section procedure.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
