The typo s/.timid/.tcid prevents to compile NuttX with
quadrature encoder configured for timer1 (CONFIG_SAMV7_TC1_QE)
and s/SAM_TC789_BASE/SAM_TC678_BASE prevented use of the
of the timer 2.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Summary:
Adding virtual evaluate platform GoldFish. Which is based on
Android Goldfish Emulator, it's a ARM virt board but Android
enhance it with more featue.
The patch set goldfish as a arm chip.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
In an implementation that supports the ARM Security Extensions, only
software executing in a Secure PL1 mode can write to CNTFRQ
Signed-off-by: hujun5 <hujun5@xiaomi.com>
This adds initialization of the ksz9477 switch when used instead of
a PHY, directly connected to SGMII
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This change fixes the issue when SAMv7 GMAC sometimes does not start packet
transmission. The issue is that EMAC_NCR_TSTART is written to EMAC_NCR register
while tx descriptor is not delivered to memory.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
According to the current implementation, "cxd56_cpu1siguninit" will only
be called once during the NuttX startup phase,
and it won't involve scenarios of multi-threaded concurrent access.
Signed-off-by: hujun5 <hujun5@xiaomi.com>
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).
This commit adds CD/DAT3 line card detection support for SAMv7 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Add a function to read PolarFire's serial number from system controller, and use the first five digits as device's mac address
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Workaround to avoid deadlock situation: The RX shall not try to wait for complete
frame in case there is RX errors detected.
In case mpfs_receive is called, it keeps waiting for complete frame and
also keeps the net_lock locked. In the mean while, the TX may run out of free
descriptors, but can not get net_lock mutex lock to be able to release used
descriptors. If there are no free TX descs it disables RX interrupts because
it may require to send response to the received frame.
So, TX side keeps RX interrupts disabled due to lack of free descriptors and
RX blocks TX to release those descs by stubbornly waiting for complete frame.
RPMSG is associated with the use of HPWORK / LPWORK queues.
After sending a message to the remote end (Linux), the system
waits for an ack before proceeding. Unfortunately this may
take sometimes more time than one would expect. Ack waiting is
also unnecessary: nothing is done with that information. Even
worse, the net_lock() is also held during the blocked time so
it blocks other network stacks that are unrelated to this.
Also reorganize the mpfs_opensbi_*.S so that the trap
handler is easily relocated in the linker .ld file without
the need to relocate the utils.S. This makes it easier to
separate the files into own segments. The trap file should be
located in the zero device.
Moreover, provide support for simultaneous ACK and message
present handling capabilities in both directions. There are
times when both bits are set but only other is being handled.
In the end, the maximum throughput of the RPMSG bus increases
easily 10-20% or even more.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commits adds support of UART2 for EPS32S3 and fixes pin mode
assignment for iomux mode
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
The master clock frequency should be multiple of the sample rate
and bit clock at the same time. Then, check if the current master
clock satisfies such a condition and set it accordingly otherwise.
In order to gracefully stop the I2S stream, add an interface to set
a `streaming` status variable that sets the `AUDIO_APB_FINAL` flag
that will be handled by the upper layers of the audio subsystem.
According to RX/TX operation, the DMA descriptors (inlink/outlink)
should be set differently. When setting the inlink, the `suc_eof`
field must be cleared by software (it will be set by hardware when
a packet is received). Similarly, the `length` field will be set
by hardware a packet is received.
Define macros used to access the registers of the GDMA channels
according to the selected channel in the header file, enabling them
to be used by other drivers.
By splitting into two different functions the setup of the DMA
descriptors and the action of loading it to the GDMA outlink
register, it enables us to "cache" DMA descriptors ready to be send
and, then, just load them whenever we are able to actually send it.
The macro `SET_BITS` only sets the bits according to the bit mask
and, once it's being used to set the address field of the GDMA
inlink/outlink register, it's necessary to clean all the bits
corresponding to that field that were eventually setup previously
to avoid messing with the bits that correspond to the current
address being setup.
This option enables architecture-specific memory copy for dynamic code loading.
For example, Ambiq has MRAM regions for instruction which can't load by
the memcpy directly.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
SiFive document: "ECC Error Handling Guide" states:
"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."
Clean the cache at this early stage so no ECC errors will be flooding later.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Check that the base address and region size are properly aligned with
relation to each other.
With NAPOT encoding the area base and size are not arbitrary, as when
the size increases the amount of bits available for encoding the base
address decreases.
Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran
This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't
change the functionality, but is the cleaner place for it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Especially the write calibration must bail out if the memory test timeouts,
otherwise the device will get stuck in running the memory test in sequence,
and it will always timeout.
Negative error value was also not properly returned from mpfs_mtc_test.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
It doesn't make sense to try to auto-determine write latency, it may pass with too low value.
Keep the existing implementation if the write latency has been set to minimum
value, otherwise just set it.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Current implementation of QSPI in SPI mode was available only for MCUs
that do not have standard SPI at all. MCUs with both QSPI and SPI can
however also use QSPI in SPI mode and thus have one more SPI bus. This
commit adds required defines and config options to support QSPI in SPI
mode for all SAMv7 MCUs.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Calculate how long an I2C transation will take in microseconds, and use
this as the timeout for mpfs_i2c_sem_waitdone.
The reason for doing this is not to keep an i2c bus reserved for the full
1 second timeout, if e.g. a sensor is not on the bus / is faulty and
non-responsive. Reading the other sensors will be blocked for a relatively
long time (1 second) in this case. This fixes such behavior.
This commit adds function pwm_set_polarity() that setups channel
polarity based on input info from application layer.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
make debug print hex again add board include
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
remove ccache, add board memory map
remove board reset
1 page might not be enough, if the task has a bigger stack. Best effort
is to allocate the default amount, however this won't work will all
tasks either.
Currently TX_FIFO_SIZE is not altered in mpfs_ep_set_fifo_size(),
but all paths (RX and TX) change MPFS_USB_RX_FIFO_SIZE only.
Fix the TX_FIFO_SIZE setup.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
After sevaral resets of the chip after programming, rptun stops working correctly.
Simple test with RPMSG UART causes a lock:
on the netcore:
nsh>cat /dev/ttyproxy
on the appcore:
nsh>echo xxx > /dev/ttyproxy
The problem doesn't occur with NRF53_FLASH_PREFETCH=n
Summary
this is a old implement for Arm64 trace but will failed
compile when enable CONFIG_SCHED_INSTRUMENTATION_SWITCH
remove it since it will never use for trace framework
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
after the follow patch:
commit 9aa57b6c53
Author: wangbowen6 <wangbowen6@xiaomi.com>
Date: Wed Mar 22 11:49:43 2023 +0800
virtio: add virtio framework in NuttX
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
(IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
support mmio transport layer, and the new framwork support
more transport layer and this commit has implemented all the
old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
configs, and update its README.txt;
New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
| | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh | 539Mbps | 524Mbps | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp | 401Mbps | 437Mbps | 583Mbps | 505Mbps |
| rv-virt:netnsh | 487Mbps | 512Mbps | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp | 387Mbps | 455Mbps | 447Mbps | 502Mbps |
| rv-virt:netnsh64 | 602Mbps | 595Mbps | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp | 414Mbps | 515Mbps | 491Mbps | 525Mbps |
| rv-virt:knetnsh64 | 515Mbps | 457Mbps | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp | 308Mbps | 389Mbps | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
Tested in QEMU 7.2.2
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This adds a config flag to remove manual bclksclk training if one wants
to just use the controller's own training.
Manual addcmd training depends on the manual bclksclk training, so this
also adds this dependency in Kconfig.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
(1)common/arm_backtrace_unwind.c:528:18: warning: 'ctrl.lr_addr' may be used uninitialized in this function [-Wmaybe-uninitialized]
(2)common/arm_backtrace_unwind.c:626:27: warning: assignment to 'long unsigned int' from 'uint8_t (*)[]' {aka 'unsigned char (*)[]'} makes integer from pointer without a cast [-Wint-conversion]
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Adds a platform specific implementation for tickless schedular operation. This includes:
- Tickless operation for vexriscv cores.
- Tickless operation for vexriscv-smp cores.
- Ticked operation for vexriscv-smp cores.
Ticked operation for vexriscv core has been refactored.
Additional default configuration added to demonstrate operation.
Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.
Considering kernel code, it's reasonable to use `PANIC()` instead
of `assert(0)` to handle with situations that require abort. Unlike
`assert`, `PANIC()` doesn't dependent on `NDEBUG`.
ESP32-S3 has only one 2.4 GHz ISM band RF module, which is shared
by Bluetooth and Wi-Fi, so Bluetooth can’t receive or transmit data
while Wi-Fi is receiving or transmitting data and vice versa.
Under such circumstances, ESP32-S3 uses the time-division
multiplexing method to receive and transmit packets.
The low-level Wi-Fi driver registers two peripheral interrupts to
the same CPU interrupt. Although the registered ISR is the same for
both peripherals interrupt, it's needed to call `up_enable_irq` to
ensure that the interrupt matrix is being set accordingly.
Please note that the current implementation of the ESP32-S3's IRQ
driver - although allow us to set a callback for each IRQ, which
represents the peripherals interrupt - doesn't allow us to call
both callbacks when these IRQs refers to a same CPU interrupt.
`g_cpu0_intmap` (or `g_cpu1_intmap`) associates each CPU interrupt
to a single IRQ/peripheral and, then, when a CPU interrupt is
triggered, only the last registered IRQ's callback will be called.
This isn't a problem here because 1) the registered callback is the
same for both IRQ's (in fact, it considers the CPU interrupt) and
2) we know in advance which peripheral interrupts will be attached
to which CPU interrupt and, then, we can set them directly.
This prevents us from getting stuck while polling the different
network structures in `devif_poll_connections`. This is useful for
Wi-Fi/Bluetooth coexistence, specifically.
- Fix macro values from `arch/xtensa/include/esp32s3/irq.h`
- Remove references to unexisting edge-triggered CPU interrupts
- Add `esp32s3_getirq` to get IRQ based on core and the `cpuint`
RTC subsystem controls not only the RTC itself but functions that
use RTC-enabled features like Bluetooth and Wi-Fi. Initialization
must be performed during the system start-up.
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting，solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.
This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion
To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization
Signed-off-by: wangming9 <wangming9@xiaomi.com>
The naming of the clang configuration file has changed after version 14
This commit will enable the compatibility with clang-14/15/16/17
Signed-off-by: chao an <anchao@xiaomi.com>
Fix buffer overflow issue from PR #10128, since the sizeof
xcpt_reg_t is different on 32/64 bit platform.
Signed-off-by: chenxiaoyi <chenxiaoyi@xiaomi.com>
Summary
Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
the change do this
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Sumary
add hostfs support for arm64, it's a copy
from arm32.
Note:
it's not support for opendir and readdir, command
like ls will not work.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
add set/get_power operation for sim_framebuffer to avoid assert
in fb_ioctl(cmd= FBIOSET_POWER/FBIOGET_POWER)
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
In armv8m the FPSCR[18:16] LTPSIZE field must be set to 0b100 for
"Tail predication not applied" as it's reset value.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
1. virtio devics/drivers match and probe/remote mechanism;
2. virtio mmio transport layer based on OpenAmp (Compatible with both
virtio mmio version 1 and 2);
3. virtio-serial driver based on new virtio framework;
4. virtio-rng driver based on new virtio framework;
5. virtio-net driver based on new virtio framework
(IOB Offload implementation);
6. virtio-blk driver based on new virtio framework;
7. Remove the old virtio mmio framework, the old framework only
support mmio transport layer, and the new framwork support
more transport layer and this commit has implemented all the
old virtio drivers;
8. Refresh the the qemu-arm64 and qemu-riscv virtio related
configs, and update its README.txt;
New virtio-net driver has better performance
Compared with previous virtio-mmio-net:
| | master/-c | master/-s | this/-c | this/-s |
| :--------------------: | :-------: | :-------: | :-----: | :-----: |
| qemu-armv8a:netnsh | 539Mbps | 524Mbps | 906Mbps | 715Mbps |
| qemu-armv8a:netnsh_smp | 401Mbps | 437Mbps | 583Mbps | 505Mbps |
| rv-virt:netnsh | 487Mbps | 512Mbps | 760Mbps | 634Mbps |
| rv-virt:netnsh_smp | 387Mbps | 455Mbps | 447Mbps | 502Mbps |
| rv-virt:netnsh64 | 602Mbps | 595Mbps | 881Mbps | 769Mbps |
| rv-virt:netnsh64_smp | 414Mbps | 515Mbps | 491Mbps | 525Mbps |
| rv-virt:knetnsh64 | 515Mbps | 457Mbps | 606Mbps | 540Mbps |
| rv-virt:knetnsh64_smp | 308Mbps | 389Mbps | 415Mbps | 474Mbps |
Note: Both CONFIG_IOB_NBUFFERS=64, using iperf command, all in Mbits/sec
Tested in QEMU 7.2.2
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
The first time interrupt nesting occurs between REE and TEE,
CURRENT_REGS needs to be set.
If TEE nesting REE breaks, then EXC_RETURN.S=0,EXC_RETURN.ES=1;
Conversely, EXC_RETURN.S=1,EXC_RETURN.ES=0;
Interrupt nesting between TEE and REE can be determined based
on the S and ES bits of EXC_RETURN.
Only once nesting between TEE and REE is supported, and cyclic
nesting between TEE and REE is not supported.
Signed-off-by: wangming9 <wangming9@xiaomi.com>
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack;
Signed-off-by: wangming9 <wangming9@xiaomi.com>
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack;
Signed-off-by: wangming9 <wangming9@xiaomi.com>
1、The process stack supports interrupt nesting, Execute in MSP;
2、The interrupt stack supports interrupt nesting;
The thread mode use PSP, and the handle mode use MSP;
3、Adjust arm_doirq、exception_common implementation to meet interrupt nesting
4、Adjust the conditions for returning MSP and PSP;
5、remove setintstack，add arm_initialize_stack;
Signed-off-by: wangming9 <wangming9@xiaomi.com>
VELAPLATFO-12536
This provides the initial hooks for Flattened Device Tree support
with QEMU RV. It also provides a new procfs file that exposes the
fdt to userspace much like the /sys/firmware/fdt endpoint in Linux.
See https://www.kernel.org/doc/Documentation/ABI/testing/sysfs-firmware-ofw
Nodes in the fdt are not yet usable by the OS.
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
Signed-off-by: liaoao <liaoao@xiaomi.com>
For TEE & REE, securefault & busfault are not banked, so the faults can
only forword to TEE/REE.
But how to crash dump the other core which not handled faults ?
Here we provide a way to resolve this problem:
1. Set the securefault & busfault to TEE
2. busfault happend from TEE, then directly dump TEE
3. busfault happend from REE, then generate nonsecurefault
4. Back to REE, and dump
Signed-off-by: ligd <liguiding1@xiaomi.com>
We can use the driver in nuttx to download
files with debugger
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: chao an <anchao@xiaomi.com>
FlexCAN before used interrupts to process incoming frames.
This patch adds a HPWORK workqueue to process incoming frames in the workqueue
context instead. Also renamed mbi to txmb for better readability.
This PR adds support for the StarFive JH7110 RISC-V SoC. This will be used by the upcoming port of NuttX for PINE64 Star64 SBC. [The source files are explained in the articles here](https://github.com/lupyuen/nuttx-star64)
Modified Files in arch/risc-v:
Kconfig: Added ARCH_CHIP_JH7110 for JH7110 SoC
New Files in arch/risc-v:
include/jh7110/chip.h: JH7110 Definitions
include/jh7110/irq.h: Support 127 External Interrupts
src/jh7110/chip.h: Interrupt Stack Macro
src/jh7110/jh7110_allocateheap.c: Kernel Heap
src/jh7110/jh7110_head.S: Linux Header and Boot Code
src/jh7110/jh7110_irq.c: Configure Interrupts
src/jh7110/jh7110_irq_dispatch.c: Dispatch Interrupts
src/jh7110/jh7110_memorymap.h: Memory Map
src/jh7110/jh7110_mm_init.c, jh7110_mm_init.h: Memory Mgmt
src/jh7110/jh7110_pgalloc.c: Page Allocator
src/jh7110/jh7110_start.c: Startup Code
src/jh7110/jh7110_timerisr.c: Timer Interrupt
src/jh7110/hardware/jh7110_memorymap.h: PLIC Base Address
src/jh7110/hardware/jh7110_plic.h: PLIC Register Addresses
src/jh7110/Kconfig: JH7110 Config
src/jh7110/Make.defs: Makefile
* Error handling for abnormal interrupts and DMA errors is now
enabled for all builds, regardless of any DEBUG configuration.
* Error handling resets the MAC for the specific errors that
may halt the Ethernet operation, instead of everything as it
was before.
The window opens when the fb opens and closes when the fb closes.
test step: run fb demo, 1. ./nuttx 2. fb
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
- Added Wi-Fi related symbols to the kernel-space linker;
- Allocate more RAM to the kernel (to be useb by the Wi-Fi driver).
- Create a specific defconfig.
Instead of setting kernel/user space instruction and data ROM as
hard-coded values on linker, set them according to the max size
of the kernel image set by CONFIG_ESP32S3_KERNEL_IMAGE_SIZE. This
is done by making KIROM, UIROM, KDROM and UDROM dependent on the
kernel size value. Also, override CONFIG_NUTTX_USERSPACE config
according to CONFIG_ESP32S3_KERNEL_IMAGE_SIZE by using a custom
PREBUILD definition.
when executing ioctl AUDIOIOC_GETBUFFERINFO,the priv->pcm is still NULL,
so it will return -ENXIO,we can remove this check at the start of ioctl
and add in the case where it is used.
Signed-off-by: shipei <shipei@xiaomi.com>
When supporting high-priority interrupts, updating the
g_running_tasks within a high-priority interrupt may be
cause problems. The g_running_tasks should only be updated
when it is determined that a task context switch has occurred.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
stack_t used by sigaltstack, make it compile sucess in sim.
Signed-off-by: yangyalei <yangyalei@xiaomi.com>
ltp: fix compile errors
Signed-off-by: yangyalei <yangyalei@xiaomi.com>
Instead of clearing the fields individually, just wipe the whole register.
This can be done because flags and rm are just parts of the fcsr.
31 8 5 0
+--------------+--------+-----------+
| | | |
| RESERVED | FRM | FSTATUS |
| | | |
+--------------+--------+-----------+
FCSR
- Save the FPU registers into the tcb so they don't get lost if the stack
frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
- Save ONLY if FPU is dirty
- Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.
Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
If the cache is already enabled before NuttX starts up,
enabling the cache in NuttX will cause the cache to be
re-invalidated, then resulting in data that is already
in the cache being flushed out.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Basically, it reserves an area of the RTC memory to preserve the
RTC timer.
Please refer to:
fa76c82a5b
This commit also removes the rtc.dummy section because C3, C6 and
H2 don't need to skip it once the region is accessed by the same
address space using the instruction and data bus.
1. add lib_fork api in libs/libc, we need a fork() api to implement the
fork relative method, such as pthread_atfork
2. rename the assembly fork entry function name to up_fork(), and rename
the up_fork() to arch specific name, such as
sim_fork()/arm_fork()/mips_fork() etc.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Clone the esp-hal-3rdparty repository and, then, checkout to a
specific version (usually indicated by the commit SHA) instead of
using a branch as the HEAD.
