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7c568f249a
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9382 Commits

Author SHA1 Message Date
Gregory Nutt
7c568f249a STM32: Various fixed to get a clean compile after integrating tickless mode. Mostly because patch came from an old version of NuttX. 2016-07-06 13:37:08 -06:00
Gregory Nutt
711f3318c5 STM32 timer: Reorganize to conform better with the NuttX coding style 2016-07-06 13:36:17 -06:00
Max Neklyudov
d8286a7f47 STM32: Add support for Tickless mode (two timer implementation) 2016-07-06 12:48:30 -06:00
Gregory Nutt
4d8213870c Freedom-K64F: Update Flash Clock divider. Flash clock must not exceed 24 Mhz 2016-07-06 12:11:26 -06:00
Gregory Nutt
c8d6707aaf Freedom-K64F: Increase MCU clock to 120MHz 2016-07-06 11:03:27 -06:00
Gregory Nutt
ba8e6083bf K64 pin mux fixes: No PIN_ALT1, use PIN_ANALOG. Remove GPIO pin mux definitions. 2016-07-02 13:22:11 -06:00
Gregory Nutt
f1d0214c61 K64 pinmap: Use uppercase to math k60 pin naming 2016-07-02 12:09:34 -06:00
Gregory Nutt
59de06f7f9 Update K64 pin multixplexing 2016-07-02 11:48:56 -06:00
Gregory Nutt
7a7998e4f9 Add support for the NXP Freedom-K64F board. This is primarily the work of Jordan Macintyre. I leveraged this code from https://github.com/jmacintyre/nuttx-k64f 2016-07-01 15:42:21 -06:00
Gregory Nutt
f73b97c3b2 arch/arm/kinetis: Completes moving register header files to kinetis/chip directory with all K64 changes. 2016-07-01 15:00:04 -06:00
Gregory Nutt
bccd2ec219 arch/arm/kinetis: Still moving register header files to kinetis/chip directory; still incorporating K64 differences. 2016-07-01 14:07:14 -06:00
Gregory Nutt
c8793637ee Add some conditional compilation to handle improper inclusion of header file 2016-07-01 13:24:31 -06:00
Gregory Nutt
4acd296926 arch/arm/kinetis: Still moving register header files to kinetis/chip directory; still incorporating K64 differences. 2016-07-01 13:15:29 -06:00
Gregory Nutt
4f64634694 arch/arm/kinetis: Still moving register header files to kinetis/chip directory; still incorporating K64 differences. 2016-07-01 12:36:09 -06:00
Gregory Nutt
62a9b10b3d arch/arm/kinetis: Still moving register header files to kinetis/chip directory; still incorporating K64 differences. 2016-07-01 11:55:15 -06:00
Gregory Nutt
91dd3306c8 arch/arm/src/kinetis: Add basic support for the K64 family. Still moving register definition files to the kinetis/chip subdirectory. 2016-07-01 11:24:41 -06:00
Gregory Nutt
71ff84b96a arch/arm/src/kinetis: Create a chip sub-directory as with other architectures. Start moving some headers... a lot more still be be moved. 2016-07-01 08:48:57 -06:00
Sebastien Lorquet
d329f117e7 Here is a missing register def for STM32L4 after support for dual RX. Thanks to Paul for porting the CAN improvements to both STM32 targets. 2016-06-30 07:11:26 -06:00
Paul A. Patience
20c611c12b STM32 CAN: Bitfield definitions should be unsigned 
Shifting 1 by 31 is undefined behaviour because 1 is signed.
We should probably use 1ul instead of 1 everywhere else,
but for now this silences a compiler warning.
 2016-06-29 13:59:33 -04:00
Paul A. Patience
52a4a20efb STM32L4 CAN: Port support for both RX FIFOs from STM32 CAN 2016-06-29 13:59:29 -04:00
Michael Spahlinger
329c760f17 SAMV7: CAN Message Filtering fixed 
- Bugfix: stdfilters didn't work because the filter was never enabled (wrong number of bits to shift)
 - Bugfix: Filters were never used because the configuration register cannot be written without using the initialization mode

Both bugs are fixed by this patch. Filtering has been tested with both standard and extended identifiers and is now working properly.
 2016-06-29 08:48:11 -06:00
Gregory Nutt
6aa067e929 Mostly costmetic changes from review of last PR 2016-06-29 07:33:30 -06:00
David Sidrane
e58b67b946 Added STM32F7 DBGMCU 2016-06-28 17:23:44 -10:00
David Sidrane
efb2850b5f STM32F7 BBSRAM fixed (and formated) flags 2016-06-28 16:28:52 -10:00
David Sidrane
eacd672ab0 STM32 BBSRAM fixed (and formated) flags 2016-06-28 16:25:04 -10:00
Gregory Nutt
8323e97201 Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #82) 
Upstream_nucleo 144
 2016-06-28 16:56:14 -06:00
Gregory Nutt
c40c107e7a STM32 F4 RTC: Fix some long lines 2016-06-28 16:55:06 -06:00
David Sidrane
edca32f40c missing s 2016-06-28 12:44:17 -10:00
David Sidrane
35ca7eaf3a Removed STM32 porting vestiges 2016-06-28 12:43:39 -10:00
Gregory Nutt
2ed1295528 Cosmetic changes from review of last PR 2016-06-28 16:42:21 -06:00
Gregory Nutt
a0a082fc03 Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #81) 
STMF7xxx RTC
 2016-06-28 16:26:31 -06:00
David Sidrane
0af47a93ae STMF7xxx RTC 
Remove proxy #defines
 Ensure the LSE(ON) etal are set and remembered in
  a) A cold start (RTC_MAGIC invalid) of the RTC
  b) A warm start (RTC_MAGIC valid) of the RTC but a clock change.

The change was needed because in bench testing a merge of the latest's STM32  53ec3ca (and friends) it became apparent that the
Sequence of operation is wrong in the reset of the Backup Domain in the RCC code.  PWR is required before the Backup Domain
can be futzed with. !!!This Code should be tested on STM32 and if needed rippled to the STM32 families
 2016-06-28 12:13:36 -10:00
Gregory Nutt
435f21225a Fix a warning about an unused label, errout: Use bool with true/false, not uint8_t with 1/0 2016-06-28 14:55:04 -06:00
Gregory Nutt
a43da4d107 STM32 CAN: Clone missing stm32_enterinitmode() and _exitinitmode() from STM32L4. Don't know if this is write but is needed to compile. 2016-06-28 14:35:49 -06:00
Gregory Nutt
93f49290a3 Eliminate a warning 2016-06-28 13:47:44 -06:00
Paul A. Patience
a4d5845887 efm32, lcp43, stm32, stm32l4: disable interrupts with NVIC_IRQ_CLEAR 2016-06-28 15:12:39 -04:00
David Sidrane
1c93e48a09 Removed STM32 porting vestiges 2016-06-28 07:13:22 -10:00
David Sidrane
e0b7708afb Fix warning 2016-06-28 07:10:11 -10:00
Gregory Nutt
c74269ced6 Significantly stylistic changes required after review of last PR 2016-06-28 09:37:21 -06:00
Gregory Nutt
725a16d033 Trivial fix to alignment 2016-06-28 09:10:32 -06:00
Gregory Nutt
0de3514af7 Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #77) 
Upstream_nucleo 144
 2016-06-28 09:07:03 -06:00
Michael Spahlinger
ed1f3aec61 Fixed build of SAMV71-XULT/nsh. With the changes from 26f7b8c the build process of the default configuration did not succeed anymore. This is fixed by this commit. 2016-06-28 08:23:41 -06:00
David Sidrane
a4040759b0 Adding PWR, RTC, BBSRAM for stm32f7 2016-06-27 16:42:01 -10:00
David Sidrane
89a79e8ac0 Double faulting on Idle task with 0 stack 2016-06-27 15:56:21 -10:00
Gregory Nutt
d4408264ec STM32 CAN fixes need to be backported to STM32L4 as well 2016-06-27 15:18:45 -06:00
Gregory Nutt
8e26d4c8e0 STM32 CAN: More fixes for compilation errors due to blind leverage of STM32L4 CAN filter IOCTLs to STM32 2016-06-27 15:16:13 -06:00
David Sidrane
6c7ea4695a Syslog changes incoperated 2016-06-27 09:59:13 -10:00
David Sidrane
02b23358e5 Update Authors 2016-06-27 09:54:28 -10:00
Gregory Nutt
738510a52c Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #75) 
Upstream_nucleo 144
 2016-06-27 12:30:53 -06:00
David Sidrane
047ea89c30 Fixed config for D1 only 2016-06-27 08:27:44 -10:00